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參數(shù)資料
| 型號(hào)： | MB86391 |
| 廠商： | Fujitsu Limited |
| 英文描述： | MPEG2 1chip Audio/Video Encoder |
| 中文描述： | 的MPEG2 1chip音頻/視頻編碼器 |
| 文件頁數(shù)： | 27/69頁 |
| 文件大小： | 847K |
| 代理商： | MB86391 |
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FUJITSU LIMITED
Proprietary and Confidential
MB86391 12, November 2001
Product Specification
Rev. 1.1
23
(d) Burst read
Fig. 3.1.1.2d: SDRAM access timing (Burst read)
(1) The external master asserts XBREQ and requests for bus privilege.
(2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to
Hi
Z and BUSDIR to 'L' (write direction and then asserts XBGRNT and XBUSEN to grant bus
privilege to the external master.
(3) The external master outputs valid data to XBMREQ, XRDWR and ADRS27:26, 17:2 and asserts
the XAS signal. Note that XBREQ must be asserted up to this cycle.
(4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT.
At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2 to
Hi
Z.
(5) The MB86391 re
outputs the address fetched in (4) to the SDRAM at the command.
(6) The MB86391 sets BUSDIR to ’H’ (read direction) to allow SDRAM read data output.
(7) The MB86391 asserts the XREADY signal during the SDRAM data read cycle and notifies it to
the external master.
(8) The MB86391 negates XBUSEN and resets to its normal state.
Notes:
The burst length is fixed to 4.
After negating XREADY, the next request for bus privilege (asserting XBREQ)
is allowed.
Burst access extending over 1 KB is not allowed.
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XAS(I/O)
XRDWR(I/O)
ADRS27:26, 17:2
(I/O)
D31:0(I/O)
XREADY(I/O)
XBUSEN(O)
BUSDIR(O)
XCS5,4,0(O)
All ‘H’
All ‘H’
All ‘H’
All ‘H’
RA
CA
CA+1
CA+2
CA+3
WD
WD+1
WD+2
WD+3
All ‘H
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