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參數資料
| 型號： | MB86391 |
| 廠商： | Fujitsu Limited |
| 英文描述： | MPEG2 1chip Audio/Video Encoder |
| 中文描述： | 的MPEG2 1chip音頻/視頻編碼器 |
| 文件頁數： | 7/69頁 |
| 文件大小： | 847K |
| 代理商： | MB86391 |
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FUJITSU LIMITED
Proprietary and Confidential
MB86391 12, November 2001
Product Specification
Rev. 1.1
3
1.3 Specification Overview
1.3.1 Major Items
Table 1.3.1 : Major items
Model
Function
Operating
frequency
Technology
Supply voltage I/O 3.0 to 3.6V, Internal 1.65 to 1.95V
Power
consumption
Operating
temperature
Package
208pin HQFP(FPT
208P
M04)
MB86391
MPEG2 1chip Audio/Video encoder
54MHz (27MHz for some)
[27MHz input clock frequency, 54MHz clock generated by internal PLL]
0.18
μ
m, Al 4 layers
T.B.D
Ta = -20 to 85
°
C
1.3.2 Function List
Table 1.3.2 : Function list
Encoding
Compliant to ISO/IEC13818
2 (MPEG2 video)MP@ML and
ISO/IEC11172
2 (MPEG1 video)
When interlacing at 29.97Hz
Compatible with size 32m
×
32n less than 720
×
480 (m, n : any integers)
When interlacing at 25Hz :
Compatible with size 32m
×
32n less than 720
×
576 (m, n : any integers)
Screen size
Video input
interface
Bit rate
Encoding method ISO/IEC11172
3 (MPEG1 audio) layer 1/2
compliant
Sampling
frequency
Channel count
2 (mono, stereo, dual, joint stereo)
Audio input
interface
Bit rate
Max. 448kbps
ISO/IEC11172
1 (MPEG1 system)
ISO/IEC13818
1 (MPEG2 system PS/TS)
[Can also output to mono media in ES and PES formats.]
Stream output
8bit parallel
Bit rate
Max. 20Mbps (CBR/VBR)
Overall controller
Internal 32bit RISC processor
SDRAM I/F for
video encoding
memory
interface
Host/SDRAM I/F
Connects two 16Mbit (1M
×
16bits) or one 64Mbit (2M
×
32bits)
Serial interface
One internal port for overall controller BOOT and command I/F
Absorbs timing errors due to disarrayed input video images by
temporarily buffering before reading video input data on an SDRAM
connected to the host/SDRAM I/F.
D1 8bit parallel, YC multiplex 8bit parallel
Video encoder
Max. 15Mbps
32kHz, 44.1kHz, 48kHz
LR multiplex serial
Audio encoder
Encoding method
Multiplexer
Connects two 16Mbit (1M
×
16bits) or one 64Mbit (2M
×
32bits)
External
Time base corrector
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