參數(shù)資料
型號(hào)： MB81V4405C-60
廠商： Fujitsu Limited
英文描述： CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 100萬(wàn)× 4位超頁(yè)模式動(dòng)態(tài)RAM的CMOS（100萬(wàn)× 4位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 26/30頁(yè)
文件大?。?/td> 348K
代理商： MB81V4405C-60
26
MB81V4405C-60/MB81V4405C-70
Fig. 19 – TEST MODE SET CYCLE (A
0
to A
9
, OE = “H” or “L”)
HIGH-Z
“H” or “L”
DQ
(Output)
V
OH
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CAS
WE
V
OL
t
RP
t
CSR
t
CPN
t
RPC
t
CHR
t
WSR
t
WHR
t
OFF
t
OH
t
RAS
t
RC
DESCRIPTION
Test Mode;
The purpose of this test mode is to reduce device test time to half of that required to test the device conventionally.
The test mode function is entered by performing a WE and CAS-before-RAS (WCBR) refresh for the entry cycle.
In the test mode, read and write operations are executed in units of eights bits which are selected by the address combination of CA
0
.
In the write mode, data is written into eight cells simultaneously. But the data must be input from all DQ pins. In the read mode, the
data of eight cells at the selected addresses are read out from DQ and checked in the following manner.
When the eight bits are all “L” or all “H”, a “H” level is output.
When the eight bits show a combination of “L” and “H”, a “L” level is output.
The test mode function is exited by performing a RAS-only refresh or a CAS-before-RAS refresh for the exit cycle.
In test mode operation, the following parameters are delayed approximately 5 ns from the specified value in the data sheet.
t
RC
, t
RWC
, t
RAC
, t
AA
, t
RAS
, t
CSH
, t
RAL
, t
RWD
, t
AWD
, t
PC
, t
PRWC
, t
CPA
, t
RHCP
, t
CPWD
相關(guān)PDF資料
PDF描述
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