參數(shù)資料
型號： MB81V4405C-60
廠商： Fujitsu Limited
英文描述： CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
中文描述： 的CMOS 100萬× 4位超頁模式動態(tài)RAM的CMOS（100萬× 4位超級頁面存取模式動態(tài)內(nèi)存）
文件頁數(shù)： 19/30頁
文件大?。?/td> 348K
代理商： MB81V4405C-60
19
MB81V4405C-60/MB81V4405C-70
t
WEZ
t
OFR
t
CAH
t
CAS
t
RCD
t
RP
Fig. 11 – HYPER PAGE MODE READ CYCLE (WE CONTROLLED)
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CAS
WE
DQ
(Input)
A
0
to A
9
V
OH
V
OL
DQ
(Output)
V
IH
V
IL
OE
DESCRIPTION
The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row
address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level
during all successive memory cycles in which the row address is latched. The address time is determined by t
CAC
, t
AA
, t
CPA
, or t
OEA
,
whichever one is the latest in occurring.
To obtain a high impedance state, confirm either of the following conditions, OE set to a high level or WE set to a low level after
CAS set to a high level or RAS and CAS set to a high level.
t
RASP
t
CRP
t
ASR
t
ASC
t
RCS
t
RHCP
“H” or “L”
ROW
ADD
COL
ADD
t
CAS
t
RSH
t
HPC
t
CAS
t
DZC
t
CAH
t
CAH
t
RAH
t
ASC
t
ASC
t
RCH
Valid Data
t
AA
t
CSH
t
RAL
HIGH-Z
HIGH-Z
t
OFF
t
OH
t
OEZ
t
OED
During one cycle is achieved, the input/output timing apply the same manner as the former cycle.
t
RDD
t
OH
t
OH
t
AA
t
CAC
t
AA
t
OEA
t
DZO
t
ON
t
RCS
t
RCH
t
WPZ
t
RCH
t
CAL
t
CAC
t
ON
t
WPZ
HIGH-Z
t
ON
t
WEZ
t
WPZ
t
CDD
t
WED
t
WEZ
t
ON
t
AR
t
RCS
COL
ADD
COL
ADD
t
CAC
t
RAC
相關(guān)PDF資料
PDF描述
MB81V4405C-70 CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
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