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參數(shù)資料
| 型號(hào)： | MB81V4400C-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 1M x 4 Bit Fast Page Mode Dynamic RAM(CMOS 1M x 4位快速頁模式動(dòng)態(tài)RAM) |
| 中文描述： | 100萬的CMOS × 4位快速頁面模式動(dòng)態(tài)RAM的CMOS（100萬× 4位快速頁模式動(dòng)態(tài)內(nèi)存） |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MB81V4400C-70 |
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5
MB81V4400C-60/MB81V4400C-70
I
RECOMMENDED OPERATING CONDITIONS
* :Undershoots of up to –2.0 volts with a pulse width not exceeding 20 ns are acceptable.
I
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty input bits are required to decode any four of 4,194,304 cell addresses in the memory matrix. Since only ten
address bits are available, the column and row inputs are separately strobed by CAS and RAS as shown in Figure
5. First, ten row address bits are input on pins A
0
-through-A
ten column address bits are input and latched with the column address strobe (CAS). Both row and column ad-
dresses must be stable on or before the falling edge of CAS and RAS, respectively. The flow-through latch type is
used for the address latch; thus, address information appearing after t
column address.
9
and latched with the row address strobe (RAS) then,
RAH
(min.)+ t
T
is automatically treated as the
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored
.
DATA INPUT
Input data is written into memory in either of three basic ways–an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch
strobe. In an early write cycle, the input data (DQ
1
-DQ
4
) is strobed by CAS and the setup/hold times are referenced
to the falling edge of CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE
goes Low after CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the falling edge
of WE.
DATA OUTPUT
The three-state buffers are LVTTL compatible with a fanout of one TTL loads. Polarity of the output data is identical
to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes
Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions:
t
RAC
:
from the falling edge of RAS when t
RCD
(max.) is satisfied.
t
CAC
:
from the falling edge of CAS when t
RCD
is greater than t
RCD
(max.).
t
AA
:
from column address input when t
RAD
is greater than t
RAD
(max.).
t
OEA
:
from the falling edge of OE when OE is brought Low after t
RAC
, t
CAC
, or t
AA
.
The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed, the
output buffers remain in a high-impedance state during the entire cycle.
FAST PAGE MODE OF OPERATION
The fast page mode of operation provides faster memory access and lower power dissipation. The fast page mode
is implemented by keeping the same row address and strobing in successive column addresses. To satisfy these
conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For each fast
page of memory, any of 1,024
×
4-bits can be accessed and, when multiple MB81V4400Cs are used, CAS is
decoded to select the desired memory fast page. Fast page mode operations need not be addressed sequentially
and combinations of read, write, and/or ready-modify-write cycles are permitted.
Parameter
Notes
Symbol
Min.
Typ.
Max.
Unit
Ambient
Operating Temp
Supply Voltage
V
CC
V
SS
V
IH
3.0
0
2.0
3.3
0
—
3.6
0
V
0
°
C to +70
°
C
Input High Voltage, all inputs
V
CC
+ 0.3
V
Input Low Voltage, all inputs*
V
IL
–0.3
—
0.8
V
1
1
1
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