參數(shù)資料
型號： MB814405D-7OL
廠商： Fujitsu Limited
英文描述： 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動(dòng)態(tài)RAM)
中文描述： 100萬× 4位超頁模式動(dòng)態(tài)RAM的CMOS（100萬× 4位超級頁面存取模式動(dòng)態(tài)內(nèi)存）
文件頁數(shù)： 26/29頁
文件大?。?/td> 596K
代理商： MB814405D-7OL
26
MB814405D-60/60L/-70/70L
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DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the functionality
of CAS-before-RAS refresh circuitry. If, after a CAS-before-RAS refresh cycle. CAS makes a transition from High to Low while RAS is
held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A
0
through A
9
are defined by the on-chip refresh counter.
Column Address: Bits A
0
through A
9
are defined by latching levels on A
0
to A
9
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows ;
1) Normalize the internal refresh address counter by using 8 RAS-only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 1,024 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-before-RAS
refresh counter test (read-modify-write cycles). Repeat this procedure 1,024 times with addresses generated by the internal
refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 1,024 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
Fig. 20 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
DQ
(Input)
DQ
(Output)
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CAS
WE
A
0
to A
9
V
OH
V
OL
V
IH
V
IL
OE
“H” or “L”
Valid Data
HIGH-Z
HIGH-Z
HIGH-Z
VALID DATA IN
COLUMN ADDRESS
t
CHR
t
RP
t
CSR
t
FRSH
t
FCAS
t
CP
t
RAL
t
FCAH
t
ASC
t
WSR
t
WHR
t
RCS
t
FCWD
t
CWL
t
RWL
t
WP
t
DH
t
DS
t
DZC
t
OED
t
FCAC
t
ON
t
OEA
t
DZO
t
OEH
t
OEZ
MB814405D-70
Min
.
—
MB814405D-60
Min.
—
Unit
Parameter
Max.
20
ns
ns
ns
ns
ns
ns
No
.
Max.
15
—
—
—
—
—
90
91
92
93
94
95
Symbol
(At recommended operating conditions unless otherwise noted.)
CAS to WE Delay Time
CAS Pulse Width
RAS Hold Time
CAS Precharge Time
10
45
15
20
10
10
40
10
15
10
Column Address Hold Time
Access Time from CAS
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
t
CPT
Note:
Assumes that CAS-before-RAS refresh counter test cycle only.
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