參數(shù)資料
型號: MB814405D-7OL
廠商: Fujitsu Limited
英文描述: 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
中文描述: 100萬× 4位超頁模式動態(tài)RAM的CMOS(100萬× 4位超級頁面存取模式動態(tài)內(nèi)存)
文件頁數(shù): 15/29頁
文件大小: 596K
代理商: MB814405D-7OL
15
MB814405D-60/60L/-70/70L
Fig. 8 – READ-MODIFY-WRITE CYCLE
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CAS
WE
DQ
(Input)
A
0
to A
9
V
OH
V
OL
DQ
(Output)
V
IH
V
IL
OE
DESCRIPTION
The read-modify-write cycle is executed by changing WE from High to Low after the data appears on the DQ pins. In the read-
modify-write cycle, OE must be changed from Low to High after the memory access time.
“H” or “L”
t
RWC
t
RAS
t
RCD
t
CRP
t
ASR
t
CAH
t
RWL
t
RCS
t
RP
t
ASC
t
RAH
t
CWL
t
DS
t
DH
t
OED
t
DZO
t
OEH
ROW
ADD
COL
ADD
t
RAD
t
CWD
VALID
DATA
t
OEZ
t
OH
t
RWD
t
AWD
t
DZC
HIGH-Z
t
CAC
t
RAC
t
AA
HIGH-Z
HIGH-Z
VALID
DATA IN
t
AR
t
ON
t
OEA
t
ON
t
WP
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