參數(shù)資料
型號： MB814405D-7OL
廠商： Fujitsu Limited
英文描述： 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
中文描述： 100萬× 4位超頁模式動態(tài)RAM的CMOS（100萬× 4位超級頁面存取模式動態(tài)內(nèi)存）
文件頁數(shù)： 23/29頁
文件大小： 596K
代理商： MB814405D-7OL
23
MB814405D-60/60L/-70/70L
Fig. 16 – RAS-ONLY REFRESH (WE = OE = “H” or “L”)
DQ
(Output)
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CAS
A
0
to A
9
V
OH
V
OL
DESCRIPTION
Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 1,024 row
addresses every 16.4-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden
refresh.
RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is
latched on the falling edge of RAS. During RAS-only refresh, DQ pins are kept in a high-impedance state.
t
RC
“H” or “L”
t
RP
t
ASR
t
RPC
HIGH-Z
t
RAH
t
CRP
t
RAS
t
OFF
ROW ADDRESS
t
CRP
t
OH
Fig. 17 – CAS-BEFORE-RAS REFRESH (ADDRESSES = OE = “H” or “L”)
DQ
(Output)
RAS
V
IH
V
IL
V
IH
V
IL
CAS
V
OH
V
OL
DESCRIPTION
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held Low
for the specified setup time (t
CSR
) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter
are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented in prep-
aration for the next CAS-before-RAS refresh operation.
WE must be held High for the specified set up time (t
WSR
) before RAS goes Low in order not to enter “Test Mode”.
“H” or “L”
t
RC
HIGH-Z
t
RAS
t
RPC
t
CPN
t
CSR
t
CHR
t
RP
t
OFF
t
OH
t
CSR
t
CPN
t
WSR
t
WHR
V
IH
V
IL
WE
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