參數(shù)資料
型號(hào)： MB814100D-70
廠(chǎng)商： Fujitsu Limited
英文描述： CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 4米× 1位快速頁(yè)面模式的DRAM（的CMOS 4米× 1位速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 5/23頁(yè)
文件大?。?/td> 238K
代理商： MB814100D-70
5
MB814100D-60/MB814100D-70
I
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty two input bits are required to decode any one of 4,194,304 cell addresses in the memory matrix. Since
only eleven address bits are available, the column and row inputs are separately strobed by CAS and RAS as
shown in Figure 5. First, eleven row address bits are input on pins A
address strobe (RAS) then, eleven column address bits are input and latched with the column address strobe
(CAS). Both row and column addresses must be stable on or before the falling edge of CAS and RAS, respectively.
The address latches are of the flow-through type; thus, address information appearing after t
automatically treated as the column address.
0
-through-A
10
and latched with the row
RAH
(min.)+ t
T
is
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of two basic ways--an early write cycle and a read-modify-write cycle.
The falling edge of WE or CAS, whichever is later, serves as the input data-latch strobe. In an early write cycle,
the input data is strobed by CAS and the setup/hold times are referenced to CAS because WE goes Low before
CAS. In a delayed write or a read-modify-write cycle, WE goes Low after CAS; thus, input data is strobed by
WE and all setup/hold times are referenced to the write-enable signal.
DATA OUTPUT
The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical
to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes
Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the following
conditions:
t
RAC
:
from the falling edge of RAS when t
RCD
t
CAC
:
from the falling edge of CAS when t
RCD
t
AA
:
from column address input when t
RAD
is greater than t
RAD
(max.).
The data remains valid until CAS returns to a High logic level. When an early write is executed, the output buffers
remain in a high-impedance state during the entire cycle.
(max.) is satisfied.
is greater than t
RCD
(max.).
FAST PAGE MODE OF OPERATION
The fast page mode of operation provides faster memory access and lower power dissipation. The fast page
mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy
these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For
each fast page of memory, any of 2,048-bits can be accessed and, when multiple MB 814100Ds are used, CAS
is decoded to select the desired memory fast page. Fast page mode operations need not be addressed
sequentially and combinations of read, write, and/or read-modify-write cycles are permitted.
相關(guān)PDF資料
PDF描述
MB814260-60 CMOS 256K ×16 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 256K ×16 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814260-70 CMOS 256K ×16 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 256K ×16 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814265-60 CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814265-70 CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814400A-60 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4M ×1 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB81416-10 制造商:Fuji Electric 功能描述:81416-10/MB
MB81416-12 制造商:Freescale Semiconductor 功能描述:81416-12
MB814400C-70PJN 制造商:FUJITSU 功能描述:Dynamic RAM, Fast Page, 1M x 4, 26 Pin, Plastic, SOJ
MB814405D-60PJN 制造商:FUJITSU Component Ltd 功能描述:
MB8146112 制造商:FUJITSU 功能描述:*
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