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參數(shù)資料
| 型號(hào)： | MB814100A-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4M ×1 位快速頁面存取模式動(dòng)態(tài)RAM) |
| 中文描述： | 的CMOS 4米× 1位快速頁面模式的DRAM的CMOS（4分× 1位快速頁面存取模式動(dòng)態(tài)內(nèi)存） |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 309K |
| 代理商： | MB814100A-70 |
11
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 5 - READ CYCLE
DESCRIPTION
The read cycle is executed by keeping both RAS and CAS “L” and keeping WE “H” throughout the cycle. The row and column addresses
are latched with RAS and CAS, respectively. The data output remains valid with CAS “L”, i.e., if CAS goes “H” , the data becomes invalid
after t
OH
is satisfied. The access time is determined by RAS (t
RAC
), CAS (t
CAC
), or Column address input (t
AA
). If t
RCD
(RAS to CAS delay
time) is greater than the specification, the access time is t
AA
.
RAS
CAS
A
0
to A
10
WE
D
OUT
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
“H” or “L”
Invalid Data
t
RC
t
RAS
t
CRP
t
CSH
t
RCD
t
RSH
t
RP
t
CAS
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CAL
t
RAL
t
RCS
ROW ADD
COLUMN ADD
t
RRH
t
RCH
t
OH
t
AA
t
CAC
t
OFF
t
RAC
HIGH-Z
VALID
DATA
t
ON
HIGH-Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB814100A-80 | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4M ×1 位快速頁面存取模式動(dòng)態(tài)RAM) |
| MB814100C-60 | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1 位快速頁面存取模式動(dòng)態(tài)RAM) |
| MB814100C-70 | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位快速頁面存取模式動(dòng)態(tài)RAM) |
| MB814100D-60 | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁面存取模式動(dòng)態(tài)RAM) |
| MB814100D-70 | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁面存取模式動(dòng)態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB81416-10 | 制造商:Fuji Electric 功能描述:81416-10/MB |
| MB81416-12 | 制造商:Freescale Semiconductor 功能描述:81416-12 |
| MB814400C-70PJN | 制造商:FUJITSU 功能描述:Dynamic RAM, Fast Page, 1M x 4, 26 Pin, Plastic, SOJ |
| MB814405D-60PJN | 制造商:FUJITSU Component Ltd 功能描述: |
| MB8146112 | 制造商:FUJITSU 功能描述:* |
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