參數(shù)資料
型號(hào)： MB8117400A-70
廠商： Fujitsu Limited
英文描述： CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 4米× 4位快速頁(yè)面模式的DRAM（的CMOS 4米× 4位快速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 24/27頁(yè)
文件大?。?/td> 304K
代理商： MB8117400A-70
24
MB8117400A-50/MB8117400A-60/MB8117400A-70
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the functionality
of CAS-before-RAS refresh circuitry. If, after a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is
held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A
0
through A
10
are defined by the on-chip refresh counter.
Column Address: Bits A
0
through A
10
are defined by latching levels on A
0
-A
10
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows ;
1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 2048 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-
before-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 2048 times with addresses
generated by the internal refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 2048 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
(At recommended operating conditions unless otherwise noted.)
“H” or “L”
Valid Data
(Output)
(Input)
HIGH-Z
HIGH-Z
t
OEH
HIGH-Z
VALID DATA IN
COLUMN ADDRESS
Fig. 16 - CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
DQ
DQ
Parameter
No.
90
91
92
93
94
35
—
35
—
50
55
50
55
—
—
—
—
77
—
70
—
Unit
ns
ns
ns
ns
ns
Min.
Max.
Min.
Max.
Min.
Max.
MB8117400A-60
MB8117400A-70
MB8117400A-50
45
—
35
—
45
45
—
—
63
—
50
—
55
—
WE
CAS
RAS
OE
Column Address Hold Time
CAS Pulse width
RAS Hold Time
Access Time from CAS
CAS to WE Delay Time
Note. Assumes that CAS-before-RAS refresh counter test cycle only.
t
FCAS
t
RP
t
CHR
t
FRSH
t
CP
t
CSR
t
ASC
t
FCAH
t
RAL
t
WSR
t
WHR
t
RCS
t
FCWD
t
CWL
t
RWL
t
WP
t
DH
t
DS
t
DZC
t
OED
FCAC
t
ON
t
OEA
t
DZO
t
OEZ
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
t
FCAC
Symbol
t
FCAH
t
FCWD
t
FCAS
t
FRSH
相關(guān)PDF資料
PDF描述
MB8117400B-50 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁(yè)面存取模式RAM)
MB8117400B-60 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁(yè)面存取模式RAM)
MB8117405A-60 CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8117405A-70 CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8117405B-50 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁(yè)面存取模式RAM)
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