
423
INDEX
logical operation instruction ................................. 401
low-power consumption mode, list of operation in101
low-power consumption mode, status transition
in ................................................................ 108
M
main function of DMA controller ........................... 308
main function of interrupt controller...................... 252
masking of other source, priority of EIT source
received and ................................................ 68
MB91110, feature of ................................................ 2
MB91110, general block diagram of ........................ 7
MB91110, memory mapping of .............................. 50
MB91110, models of ................................................ 6
memory access, operation mode related to......... 109
memory load instruction ....................................... 403
memory mapping ................................................... 26
memory mapping of FR series, common ............... 50
memory mapping of MB91110............................... 50
memory store instruction...................................... 404
minimum effective pulse width of input into DREQ0 to
DREQ2 ...................................................... 342
mode 0, UART interrupt and flag setting timing
reception in ................................................ 301
mode 1, UART interrupt and flag setting timing
reception in ................................................ 301
mode 2, UART interrupt and flag setting timing
reception in ................................................ 302
mode data ............................................................ 110
mode pin .............................................................. 110
mode register (MODR)......................................... 110
mode register (MODR) write, note on .................. 111
modes 0 to 2, UART interrupt and flag setting timing
(transmission in) ........................................ 302
monitor debugger, emulator/ ................................ 392
multiplication and division Instruction................... 402
N
NMI control section, block diagram of external
interrupt/..................................................... 240
NMI control section, register of external interrupt/ 240
NMI processing .................................................... 245
NMI, processing of user interrupt/ .......................... 70
no delay slot, branch instruction with ..................... 57
no delay slot, operation of branch instruction with . 57
no error detection................................................. 391
non-maskable interrupt (NMI) .............................. 260
note on EIT ............................................................ 59
note on mode register (MODR) write ................... 111
note on UART use ............................................... 304
note on using A/D converter .................................281
O
one-shot mode timing chart ..................................235
operating frequencies by clock doubler function
on/off, combination of ...................................95
operation of branch instruction with delay slot........54
operation of branch instruction with no delay slot...57
option specifying -K lib option when using
character string operation function .............387
ordinary branch (no delay) instruction ..................405
ordinary bus sccess..............................................160
ordinary DRAM interface, automatic wait cycle
timing of ......................................................182
ordinary DRAM interface, read cycle timing of .....174
ordinary DRAM interface, write cycle timing of .....176
ordinary DRAM read cycle timing .........................178
ordinary DRAM write cycle timing.........................180
other instruction ....................................................407
output pin function ................................................222
P
peripheral clock, block using ..................................88
Pin function, explanation of ....................................10
pin status list, term used in ...................................378
PLL clock setting, example of.................................96
PLL control register (PCTR) ...................................84
port data register (PDR) .......................................205
port direction register (DDR).................................206
PPG timer function ...............................................226
PPG timer interrupt resource and timing chart
(PPG output is ordinary polarity) ................237
PPG timer module configuration...........................226
PPG timer, block diagram of.................................227
PPG timer, register of ...........................................228
precaution on clock doubler function on/off ............95
priority judgment ...................................................258
program access ......................................................49
program status register (PS) ..................................44
PWM mode timing chart .......................................233
R
read cycle timing in each mode ............................167
read cycle timing of hyper DRAM interface ..........190
read cycle timing of ordinary DRAM interface ......174
read cycle timing of single DRAM interface ..........187
read-write cycle timing..........................................171
refresh control register (RFCR) ............................131
reset defer method .................................................85