
xviii
Table 10.3-1
Values of Interrupt Level Setting Bits and Their Corresponding Interrupt Levels .................. 256
Table 10.4-1
Interrupt Resources, Numbers, and Levels ........................................................................... 258
Table 10.6-1
Cancel-applicable Interrupt Levels ........................................................................................ 262
Table 11.3-1
Selection of A/D Converter Activation Resources ................................................................. 272
Table 11.3-2
Specifying A/D Converter Operation Mode ............................................................................ 273
Table 11.3-3
Setting of A/D conversion start channel ................................................................................. 274
Table 11.3-4
Setting of A/D conversion end channel .................................................................................. 274
Table 12.3-1
Selection of UART Operation Mode ...................................................................................... 287
Table 12.3-2
Selection of Clock Source ...................................................................................................... 287
Table 12.3-3
Machine Clock Dividing Ratios ............................................................................................... 294
Table 12.4-1
UART Operation Modes ........................................................................................................ 295
Table 12.4-2
Baud Rates (Asynchronous Mode) ........................................................................................ 295
Table 12.4-3
Baud Rates (CLK Synchronous Mode) .................................................................................. 296
Table 12.4-4
Baud Rates and Reload Values (Asynchronous) .................................................................. 296
Table 13.3-1
Stop or End Resources of DMA Transfer .............................................................................. 312
Table 13.3-2
DMA Transfer End Signal Output Timings ............................................................................ 313
Table 13.3-3
DMA Transfer Request Acknowledge Signal Output Timings
.............................................. 314
Table 13.3-4
Detection Levels at the External Transfer Request Input Pins .............................................. 314
Table 13.3-5
DMA Transfer Resources ...................................................................................................... 315
Table 13.3-6
Transfer Data Width ............................................................................................................... 315
Table 13.3-7
DMA Destination Address Count Modes ............................................................................... 318
Table 13.3-8
DMA Source Address Count Modes ...................................................................................... 318
Table 13.4-1
Selection of Transfer Stop Request ....................................................................................... 338
Table 13.4-2
Selection of Inter-channel Priority Order Mode ...................................................................... 341
Table 13.4-3
DACK Output Timings ........................................................................................................... 346
Table 13.4-4
DEOP Output Timings ........................................................................................................... 346
Table 14.3-1
Relationships between Detection Positions and Return Values ............................................ 356
Table A-1
I/O Mapping ........................................................................................................................... 367
Table B-1
Interrupt Vectors .................................................................................................................... 375
Table C-1
Terms Used in the Pin Status List ......................................................................................... 378
Table C-2
Pin Status (16-bit External Bus, 2CAS1WR Mode) ............................................................... 379
Table C-3
Pin Status (16-bit External Bus, 1CAS2WR Mode) ............................................................... 381
Table C-4
Pin Status (8-bit External Bus) ............................................................................................... 383
Table E-1
Meanings of the Addressing Mode Symbols ......................................................................... 395
Table E-2
Instruction format ................................................................................................................... 397
Table E.1-1
Addition and Subtraction Instructions .................................................................................... 400
Table E.1-2
Compare Operation Instructions ............................................................................................ 400
Table E.1-3
Logical Operation Instructions ............................................................................................... 401