
xvi
Figure 13.4-3
Continuous Transfer Sequence .............................................................................................. 327
Figure 13.4-4
Step Transfer Sequence ......................................................................................................... 327
Figure 13.4-5
Block Transfer Sequence ....................................................................................................... 328
Figure 13.4-6
DMA Transfer Control Timings ............................................................................................... 333
Figure 13.4-7
Inter-channel Priority Order in Fixed Mode ............................................................................. 340
Figure 13.4-8
Inter-channel Priority Order in Fixed Mode ............................................................................. 341
Figure 13.4-9
Shortest Timing from DREQ Negation until Transfer Stop (External Source) ........................ 342
Figure 13.4-10 Shortest Timing from DREQ Negation until Transfer Stop (External Source and Destination) 343
Figure 13.4-11 Shortest Timing from DREQ0/1/2 Input until Transfer Start ................................................... 343
Figure 13.4-12 Step Transfer Timings ............................................................................................................ 344
Figure 13.4-13 Block Transfer Timings ........................................................................................................... 344
Figure 13.4-14 Step Transfer Timings ............................................................................................................ 345
Figure 13.4-15 Block Transfer Timings ........................................................................................................... 345
Figure 13.4-16 AC Timing of DREQ Input ....................................................................................................... 347
Figure 14.1-1
Block Diagram of the Bit Search Module ................................................................................ 352
Figure 14.1-2
Registers of the Bit Search Module ........................................................................................ 352
Figure 15.3-1
I-ROM/RAM Memory Mapping in Ordinary Operation ............................................................ 362
Figure 15.3-2
I-ROM/RAM Memory Mapping in I-RAM Write Mode ............................................................. 363