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| 型號(hào)： | MAX9260GCB/V+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER GMSL 64TQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | * |
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Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
14 _____________________________________________________________________________________
MAX9260 Pin Description (continued)
PIN
NAME
FUNCTION
18
TX/SCL
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI
pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In
I2C mode, TX/SCL is the SCL output of the MAX9260’s I2C master.
19
PWDN
Power-Down. Active-low power-down input requires external pulldown or pullup resis-
tors.
20
ERR
Error. Active-low open-drain video data error output with internal pullup to IOVDD.
ERR goes low when the number of decoding errors during normal operation exceed a
programmed error threshold or when at least one PRBS error is detected during PRBS
test. ERR is high impendence when PWDN = low.
21, 31, 50, 60
IOGND
Input/Output Ground
22
LOCK
Open-Drain Lock Output with Internal Pullup to IOVDD. LOCK = high indicates PLLs
are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs
are not locked or incorrect serial-word-boundary alignment. LOCK remains low when
the configuration link is active. LOCK is high impedance when PWDN = low.
23
WS
Word Select. I2S word-select output.
24
SCK
Serial Clock. I2S serial-clock output
25
SD
Serial Data. I2S serial-data output. Disable I2S to use SD as an additional data output
latched on the selected edge of PCLKOUT.
26–29, 32–40,
42–49, 52–59
DOUT0–
DOUT27,
DOUT28/MCLK
Data Output[0:28]. Parallel data outputs. Output data can be strobed on the selected
edge of PCLKOUT. Set BWS = low (24-bit mode) to use DOUT0–DOUT20 (RGB and
SYNC). DOUT21–DOUT28 are not used in 24-bit mode and are set to low. Set BWS =
high (32-bit mode) to use DOUT0–DOUT28 (RGB, SYNC, and two extra outputs).
DOUT28 can be used to output MCLK (see the Additional MCLK Output for Audio
Applications section).
30, 51
IOVDD
1.8V to 3.3V Logic I/O Power Supply. Bypass IOVDD to IOGND with 0.1FF and 0.001FF
capacitors as close as possible to the device with the smaller value capacitor closest
to IOVDD.
41
PCLKOUT
Parallel Clock Output. Used for DOUT0–DOUT28.
61
SSEN
Spread-Spectrum Enable. Parallel output spread-spectrum enable input requires
external pulldown or pullup resistors. The state of SSEN latches upon power-up or
when resuming from power-down mode (PWDN = low). Set SSEN = high for Q2%
spread spectrum on the parallel outputs. Set SSEN = low to use the parallel outputs
without spread spectrum.
62
DRS
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit
mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data
rates of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
—
EP
Exposed Pad. EP internally connected to AGND. MUST externally connect EP to the
AGND plane to maximize thermal and electrical performance.
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| MAX9263EVKIT+ | 制造商:Maxim Integrated Products 功能描述:GMSL SERIALIZER WITH HDCP - Boxed Product (Development Kits) |
| MAX9263GCB/V+ | 功能描述:串行器/解串器 - Serdes GMSL Serializer w/HDCP Interface RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9263GCB/V+T | 功能描述:串行器/解串器 - Serdes GMSL Serializer w/HDCP Interface RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9264EVKIT+ | 制造商:Maxim Integrated Products 功能描述:GMSL DESERIALIZER WITH HDCP - Boxed Product (Development Kits) |
| MAX9264GCB/V+ | 功能描述:串行器/解串器 - Serdes GMSL Deserializer w/HDCP Interface RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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