參數(shù)資料
型號： MAX9260GCB/V+T
廠商： Maxim Integrated Products
文件頁數(shù)： 34/51頁
文件大?。?/td> 0K
描述： IC DESERIALIZER GMSL 64TQFP
標準包裝： 750
系列： *
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
4 ______________________________________________________________________________________
MAX9259 AC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARALLEL CLOCK INPUT (PCLKIN)
Clock Frequency
fPCLKIN
VBWS = VGND, VDRS = VIOVDD
8.33
16.66
MHz
VBWS = VGND, VDRS = VGND
16.66
104
VBWS = VIOVDD, VDRS = VIOVDD
6.25
12.5
VBWS = VIOVDD, VDRS = VGND
12.5
78
Clock Duty Cycle
DC
tHIGH/tT or tLOW/tT (Figure 5)
35
50
65
%
Clock Transition Time
tR, tF
(Figure 5)
4
ns
Clock Jitter
tJ
3.125Gbps, 300kHz sinusoidal jitter
800
ps(P-P)
I2C/UART PORT TIMING (Note 3)
Output Rise Time
tR
30% to 70%, CL = 10pF to 100pF, 1kI
pullup to IOVDD
20
150
ns
Output Fall Time
tF
70% to 30%, CL = 10pF to 100pF, 1kI
pullup to IOVDD
20
150
ns
Input Setup Time
tSET
I2C only (Figure 6)
100
ns
Input Hold Time
tHOLD
I2C only (Figure 6)
0
ns
SWITCHING CHARACTERISTICS (Note 3)
Differential Output Rise-and-Fall
Time
tR, tF
20% to 80%, VOD ≥ 400mV, RL = 100I,
serial-data rate = 3.125Gbps
90
150
ps
Total Serial Output Jitter
tTSOJ1
3.125Gbps PRBS signal, measured at
VOD = 0V differential, preemphasis
disabled (Figure 7)
0.25
UI
Deterministic Serial Output Jitter
tDSOJ2
3.125Gbps PRBS signal
0.15
UI
Parallel Data Input Setup Time
tSET
(Figure 8)
1
ns
Parallel Data Input Hold Time
tHOLD
(Figure 8)
1.5
ns
Serializer Delay (Note 4)
tSD
(Figure 9)
Spread spectrum enabled
2830
Bits
Spread spectrum disabled
270
Link Start Time
tLOCK
(Figure 10)
3.5
ms
Power-Up Time
tPU
(Figure 11)
3.5
ms
I2S INPUT TIMING
WS Frequency
fWS
(Table 4)
8
192
kHz
Sample Word Length
nWS
(Table 4)
4
32
Bits
SCK Frequency
fSCK
fSCK = fWS x nWS x 2
(8 x 4)
x 2
(192 x
32) x 2
kHz
SCK Clock High Time (Note 3)
tHC
VSCK ≥ VIH, tSCK = 1/fSCK
0.35 x
tSCK
ns
SCK Clock Low Time (Note 3)
tLC
VSCK ≤ VIL, tSCK = 1/fSCK
0.35 x
tSCK
ns
SD, WS Setup Time
tSET
(Figure 12, Note 3)
2
ns
SD, WS Hold Time
tHOLD
(Figure 12, Note 3)
2
ns
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