參數(shù)資料
型號: MAX9260GCB/V+T
廠商: Maxim Integrated Products
文件頁數(shù): 36/51頁
文件大?。?/td> 0K
描述: IC DESERIALIZER GMSL 64TQFP
標(biāo)準(zhǔn)包裝: 750
系列: *
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
______________________________________________________________________________________ 41
slow. The MAX9259/MAX9260 support I2C/UART rates
up to 1Mbps.
AC-Coupling
AC-coupling isolates the receiver from DC voltages up to
the voltage rating of the capacitor. Four capacitors—two
at the serializer output and two at the deserializer input—
are needed for proper link operation and to provide
protection if either end of the cable is shorted to a high
voltage. AC-coupling blocks low-frequency ground shifts
and low-frequency common-mode noise.
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start
from different voltage levels. Because the transition time
is finite, starting the signal transition from different volt-
age levels causes timing jitter. The time constant for an
AC-coupled link needs to be chosen to reduce droop
and jitter to an acceptable level. The RC network for an
AC-coupled link consists of the CML receiver termination
resistor (RTR), the CML driver termination resistor (RTD),
and the series AC-coupling capacitors (C). The RC time
constant for four equal-value series capacitors is (C x
(RTD + RTR))/4. RTD and RTR are required to match the
transmission line impedance (usually 100I). This leaves
the capacitor selection to change the system time con-
stant. Use at least 0.2FF (100V) high-frequency surface-
mount ceramic capacitors to pass the lower speed
reverse-channel signal. Use capacitors with a case size
less than 3.2mm x 1.6mm to have lower parasitic effects
to the high-speed signal.
Power-Supply Circuits and Bypassing
The MAX9259 uses an AVDD and DVDD of 1.7V to 1.9V.
The MAX9260 uses an AVDD and DVDD of 3.0V to 3.6V.
All single-ended inputs and outputs on the MAX9259/
MAX9260 derive power from an IOVDD of 1.7V to 3.6V.
The input levels or output levels scale with IOVDD.
Proper voltage-supply bypassing is essential for high-
frequency circuit stability.
Cables and Connectors
Interconnect for CML typically has a differential imped-
ance of 100I. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Twisted-pair and shielded twisted-pair
cables offer superior signal quality compared to ribbon
cable and tend to generate less EMI due to magnetic-
field canceling effects. Balanced cables pick up noise
as common mode rejected by the CML receiver. Table
17 lists the suggested cables and connectors used in
the GMSL link.
Board Layout
Separate the parallel signals and CML high-speed serial
signals to prevent crosstalk. Use a four-layer PCB with
separate layers for power, ground, CML, and digital
signals. Layout PCB traces close to each other and have
a 100I differential characteristic impedance. The trace
dimensions depend on the type of trace used (microstrip
or stripline). Note that two 50I PCB traces do not
have 100I differential impedance when brought close
together—the impedance goes down when the traces
are brought closer.
Route the PCB traces for a CML channel (there are two
conductors per CML channel) in parallel to maintain the
differential characteristic impedance. Avoid vias. If vias
must be used, use only one pair per CML channel and
place the via for each line at the same point along the
length of the PCB traces. This way, any reflections occur
at the same time. Do not make vias into test points for
Table 17. Suggested Connectors and Cables for GMSL
SUPPLIER
CONNECTOR
CABLE
JAE Electronics, Inc.
MX38-FF
A-BW-Lxxxxx
Nissei Electric Co., Ltd.
GT11L-2S
F-2WME AWG28
Rosenberger Hochfrequenztechnik GmbH
D4S10A-40ML5-Z
Dacar 538
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