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參數(shù)資料
| 型號： | MAX5866ETM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANLG FRONT END 60MSPS 48-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 4 |
| 功率（瓦特）： | 2.10W |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.3 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.3 V |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-TQFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
Shutdown mode offers the most dramatic power sav-
ings by shutting down all the analog sections of the
MAX5866 and placing the ADCs’ digital outputs in tri-
state mode. When the ADCs’ outputs transition from tri-
state to on, the last converted word is placed on the
digital outputs. The DACs’ digital bus inputs must be
zero or OVDD because the bus is not internally pulled
up. The DACs’ previously stored data is lost when com-
ing out of shutdown mode. The wake-up time from shut-
down mode is dominated by the time required to
charge the capacitors at REFP, REFN, and COM. In
internal reference mode and buffered external refer-
ence mode, the wake-up time is typically 40s to enter
Xcvr mode, 10s to enter Rx mode, and 40s to enter
Tx MODE.
In idle mode, the reference and clock distribution cir-
cuits are powered, but all other functions are off. The
ADCs’ outputs are forced to tri-state. The DACs’ digital
bus inputs must be zero or OVDD, because the bus is
not internally pulled up. The wake-up time required for
the device to become fully operational from idle mode
is 10s. When the ADCs’ outputs transition from tri-state
to on, the last converted word is placed on the digital
outputs. In the idle mode, the supply current is lowered
if the clock input is set to zero or OVDD; however, the
wake-up time extends to 40s.
In standby mode, only the ADCs’ reference is powered;
the rest of the device’s functions are off. The pipeline
ADCs are off and DA0 to DA7 are in tri-state mode. The
DACs’ digital bus inputs must be zero or OV DD
because the bus is not internally pulled up. The wake-
up time from standby mode to the Xcvr mode is domi-
nated by the 40s required to activate the pipeline
ADCs and DACs. When the ADC outputs transition from
tri-state to active, the last converted word is placed on
the digital outputs.
The serial digital interface is a standard 3-wire connec-
tion compatible with SPI/QSPI/MICROWIRE/DSP
interfaces. Set CS low to enable the serial data loading
at DIN. Following the CS high-to-low transition, data is
shifted synchronously, MSB first, on the rising edge of
the serial clock (SCLK). After 8 bits are loaded into the
serial input register, data is transferred to the latch. CS
must transition high for a minimum of 80ns before the
next write sequence. The SCLK can idle either high or
low between transitions. Figure 5 shows the detailed
timing diagram of the 3-wire serial interface.
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
______________________________________________________________________________________
17
QSPI is a trademark of Motorola, Inc.
Table 3. MAX5866 Operation Modes
FUNCTION
DESCRIPTION
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
Shutdown
Device shutdown. REF is off, ADCs are
off, and the ADC bus is tri-stated; DACs
are off and the DAC input bus must be
set to zero or OVDD.
XX
X
0
Idle
REF and CLK are on, ADCs are off,
and the ADC bus is tri-stated; DACs
are off and the DAC input bus must be
set to zero or OVDD.
XX
X
0
1
Rx
REF is on, ADCs are on; DACs are off,
and the DAC input bus must be set to
zero or OVDD.
XX
X
0
1
0
Tx
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are on.
XX
X
0
1
Xcvr
REF is on, ADCs and DACs are on.
X
1
0
Standby
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are off and the
DAC input bus must be set to zero or
OVDD.
XX
X
1
0
1
X = Don’t care.
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