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參數(shù)資料
| 型號： | MAX5866ETM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANLG FRONT END 60MSPS 48-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 4 |
| 功率（瓦特）： | 2.10W |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.3 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.3 V |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
MAX5866
DAC Timing
Figure 4 shows the relationship between the clock, input
data, and analog outputs. Data for the I channel is
latched on the falling edge of the clock signal, and Q-
channel data is latched on the rising edge of the clock
signal. Both I and Q outputs are simultaneously updated
on the next rising edge of the clock signal.
3-Wire Serial Interface and
Operation Modes
The 3-wire serial interface controls the MAX5866 opera-
tion modes. Upon power-up, the MAX5866 must be pro-
grammed to operate in the desired mode. Use the 3-wire
serial interface to program the device for the shutdown,
idle, standby, Rx, Tx, or Xcvr mode. An 8-bit data register
sets the operation modes as shown in Table 3. The serial
interface remains active in all six modes.
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
16
______________________________________________________________________________________
Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC =
1.024V, External Reference Mode VREFDAC = VREFIN)
DIFFERENTIAL OUTPUT VOLTAGE
OFFSET BINARY
(DD0–DD9)
INPUT DECIMAL CODE
11 1111 1111
1023
11 1111 1110
1022
10 0000 0001
513
10 0000 0000
512
01 1111 1111
511
00 0000 0001
1
00 0000 0000
0
VREFDAC
2.56
1023
×
VREFDAC
2.56
1021
1023
×
VREFDAC
2.56
3
1023
×
VREFDAC
2.56
1
1023
×
VREFDAC
2.56
1
1023
×
VREFDAC
2.56
1021
1023
×
VREFDAC
2.56
1023
×
Figure 4. DAC System Timing Diagram
tDSQ
tDSI
Q: N - 2
I: N - 1
DD0–DD9
CLK
ID
QD
Q: N - 1
I: N
Q: N
I: N + 1
N - 2
N - 1
N
N - 2
N - 1
N
tDHQ
tDHI
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