參數(shù)資料
型號： MAX5866ETM+T
廠商： Maxim Integrated Products
文件頁數(shù)： 22/26頁
文件大?。?/td> 0K
描述： IC ANLG FRONT END 60MSPS 48-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
通道數(shù)： 4
功率（瓦特）： 2.10W
電壓 - 電源，模擬： 2.7 V ~ 3.3 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.3 V
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-TQFN-EP（7x7）
包裝： 帶卷 (TR)
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input ampli-
tude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F,
Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC ANALOG OUTPUT
Full-Scale Output Voltage
VFS
±400
mV
Output Common-Mode Range
1.29
1. 5
V
ADC-DAC INTERCHANNEL CHARACTERISTICS
ADC-DAC Isolation
ADC fINI = fINQ = 25MHz, DAC fOUTI =
fOUTQ = 6MHz, fCLK = 60MHz
70
dB
ADC-DAC TIMING CHARACTERISTICS
CLK Rise to I-ADC Channel-I
Output Data Valid
tDOI
Figure 3 (Note 4)
3
4.9
8.5
ns
CLK Fall to Q-ADC Channel-Q
Output Data Valid
tDOQ
Figure 3 (Note 4)
3
6.2
8.5
ns
I-DAC Data to CLK Fall Setup
Time
tDSI
Figure 4 (Note 4)
9
ns
Q-DAC Data to CLK Rise Setup
Time
tDSQ
Figure 4 (Note 4)
9
ns
CLK Fall to I-DAC Data Hold Time
tDHI
Figure 4 (Note 4)
-3
ns
CLK Rise to Q-DAC Data Hold Time
tDHQ
Figure 4 (Note 4)
-3
ns
Clock Duty Cycle
50
%
CLK Duty-Cycle Variation
±10
%
Digital Output Rise/Fall Time
20% to 80%
2.0
ns
SERIAL INTERFACE TIMING CHARACTERISTICS
Falling Edge of CS to Rising Edge
of First SCLK Time
tCSS
Figure 5 (Note 4)
10
ns
DIN to SCLK Setup Time
tDS
Figure 5 (Note 4)
10
ns
DIN to SCLK Hold Time
tDH
Figure 5 (Note 4)
0
ns
SCLK Pulse-Width High
tCH
Figure 5 (Note 4)
25
ns
SCLK Pulse-Width Low
tCL
Figure 5 (Note 4)
25
ns
SCLK Period
tCP
Figure 5 (Note 4)
50
ns
SCLK to CS Setup Time
tCS
Figure 5 (Note 4)
0
ns
CS High Pulse Width
tCSW
Figure 5 (Note 4)
80
ns
MODE RECOVERY TIMING CHARACTERISTICS
From shutdown to Rx mode, Figure 6, ADC
settles to within 1dB
10
Shutdown Wake-Up Time
tWAKE,SD
From shutdown to Tx mode, Figure 6, DAC
settles to within 10 LSB error
40
s
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