參數(shù)資料
型號： MAX5866ETM+T
廠商： Maxim Integrated Products
文件頁數(shù)： 24/26頁
文件大?。?/td> 0K
描述： IC ANLG FRONT END 60MSPS 48-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
通道數(shù)： 4
功率（瓦特）： 2.10W
電壓 - 電源，模擬： 2.7 V ~ 3.3 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.3 V
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-TQFN-EP（7x7）
包裝： 帶卷 (TR)
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
_______________________________________________________________________________________
7
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input ampli-
tude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F,
Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Threshold
VINL
DD0–DD9, CLK, SCLK, DIN, CS
0.3 x
OVDD
V
Input Leakage
DIIN
DD0–DD9, CLK, SCLK, DIN, CS = OGND or
OVDD
±5A
Input Capacitance
DCIN
5pF
DIGITAL OUTPUTS (DA0–DA7)
Output Voltage Low
VOL
ISINK = 200A
0.2 x
OVDD
V
Output Voltage High
VOH
ISOURCE = 200A
0.8 x
OVDD
V
Tri-State Leakage Current
ILEAK
±5A
Tri-State Output Capacitance
COUT
5pF
Note 1: Specifications from TA = +25°C to +85°C are guaranteed by production tests. Specifications from TA = +25°C to -40°C are
guaranteed by design and characterization.
Note 2: The minimum clock frequency for the MAX5866 is 40MHz.
Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 4: Guaranteed by design and characterization.
Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec-
ond channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tone bins.
Note 6: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
Typical Operating Characteristics
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 60MHz 50% duty cycle, ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM =
0.33F, Xcvr mode, TA = +25°C, unless otherwise noted.)
-110
-70
-90
-30
-50
-10
-80
-100
-40
-60
-20
0
05
10
15
20
25
30
ADC CHANNEL-IA FFT PLOT
MAX5866
toc01
FREQUENCY (MHz)
AMPLITUDE
(dBFS)
fCLK = 60MHz
fIA = 12.499MHz
fQA = 19.99MHz
IA
QA
HD3
HD2
-110
-70
-90
-30
-50
-10
-80
-100
-40
-60
-20
0
ADC CHANNEL-QA FFT PLOT
MAX5866
toc02
FREQUENCY (MHz)
AMPLITUDE
(dBFS)
05
10
15
20
25
30
fCLK = 60MHz
fIA = 12.499MHz
fQA = 19.99MHz
HD3
HD2
IA
QA
-110
-70
-90
-30
-50
-10
-80
-100
-40
-60
-20
0
ADC CHANNEL-IA TWO-TONE FFT PLOT
MAX5866
toc03
FREQUENCY (MHz)
AMPLITUDE
(dBFS)
05
10
15
20
25
30
fCLK = 60MHz
f1 = 11.813MHz
f2 = 12.795MHz
AIA = -7dBFS PER TONE
f1
f2
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