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參數(shù)資料
| 型號： | MAX5866ETM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANLG FRONT END 60MSPS 48-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 4 |
| 功率（瓦特）： | 2.10W |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.3 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.3 V |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
22
___________________________________________________________________________________________________
0
2
1
4
3
7
6
5
000
010
001
011
100
101
110
AT STEP
011 (1/2 LSB )
AT STEP
001 (1/4 LSB )
111
DIGITAL INPUT CODE
ANALOG
OUTPUT
VALUE
Figure 12a. Integral Nonlinearity
0
2
1
4
3
6
5
000
010
001
011
100
101
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
1 LSB
DIGITAL INPUT CODE
ANALOG
OUTPUT
VALUE
Figure 12b. Differential Nonlinearity
Figure 11 illustrates the MAX5866 working with the
MAX2820 in TDD mode to provide a complete 802.11b
radio front-end solution. Because the MAX5866 DAC has
full differential analog outputs with a common-mode level
of 1.4V, and the ADC has wide-input common-mode
range, it can interface directly with RF transceivers while
eliminating discrete components and amplifiers used for
level-shifting circuits. Also, the DAC’s full dynamic range
is preserved because the internally generated common-
mode level eliminates code-generated level shifting or
attenuation due to resistor level shifting. The MAX5866
ADC has 1VP-P full-scale range and accepts input com-
mon-mode levels of VDD / 2 (±200mV). These features
simplify the analog interface between RF quadrature
demodulator and ADC while eliminating discrete gain
amplifiers and level-shifting components.
Grounding, Bypassing, and
Board Layout
The MAX5866 requires high-speed board layout design
techniques. Refer to the MAX5865 EV kit data sheet for
a board layout reference. Locate all bypass capacitors
as close to the device as possible, preferably on the
same side of the board as the device, using surface-
mount devices for minimum inductance. Bypass VDD to
GND with a 0.1F ceramic capacitor in parallel with a
2.2F capacitor. Bypass OVDD to OGND with a 0.1F
ceramic capacitor in parallel with a 2.2F capacitor.
Bypass REFP, REFN, and COM each to GND with a
0.33F ceramic capacitor. Bypass REFIN to GND with
a 0.1F capacitor.
Multilayer boards with separated ground and power
planes yield the highest level of signal integrity. Use a
split ground plane arranged to match the physical loca-
tion of the analog ground (GND) and the digital output
driver ground (OGND) on the device package. Connect
the MAX5866 exposed backside paddle to the GND
plane. Join the two ground planes at a single point so
the noisy digital ground currents do not interfere with
the analog ground plane. The ideal location for this
connection can be determined experimentally at a
point along the gap between the two ground planes.
Make this connection with a low-value, surface-mount
resistor (1 to 5), a ferrite bead, or a direct short.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy digital system’s ground plane (e.g.,
downstream output buffer or DSP ground plane).
Route high-speed digital signal traces away from sensi-
tive analog traces. Make sure to isolate the analog
input lines to each respective converter to minimize
channel-to-channel crosstalk. Keep all signal lines short
and free of 90° turns.
Dynamic Parameter Definitions
ADC and DAC Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the device are measured using
the end-point method. (DAC Figure 12a).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes (ADC) and a monotonic transfer function
(ADC and DAC) (DAC Figure 12b).
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