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參數(shù)資料
| 型號： | MAX1304ECM/V+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 4000KSPS 8CH 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 3.65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.82W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
14
______________________________________________________________________________________
Pin Description (continued)
PIN
MAX1304
MAX1308
MAX1312
MAX1305
MAX1309
MAX1313
MAX1306
MAX1310
MAX1314
NAME
FUNCTION
20
REF+
Positive Reference Bypass. Bypass REF+ with a 0.1F capacitor to AGND. Also
bypass REF+ to REF- with a 2.2F and a 0.1F capacitor.
VREF+ = VCOM + VREF/2.
21
COM
Reference Common Bypass. Bypass COM to AGND with a 2.2F and a 0.1F
capacitor. VCOM = 13/25 x AVDD.
22
REF-
Negative Reference Bypass. Bypass REF- with a 0.1F capacitor to AGND.
Also bypass REF- to REF+ with a 2.2F and a 0.1F capacitor.
VREF- = VCOM - VREF/2.
24, 39
DGND
Digital Ground. DGND is the power return for DVDD. Connect all DGND
pins together.
25, 38
DVDD
Digital Power Input. DVDD powers the digital section of the converter, including
the parallel interface. Apply +2.7V to +5.25V to DVDD. Bypass DVDD to DGND
with a 0.1F capacitor. Connect all DVDD pins together.
26
D0
Digital I/O 0 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
27
D1
Digital I/O 1 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
28
D2
Digital I/O 2 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
29
D3
Digital I/O 3 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
30
D4
Digital I/O 4 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
31
D5
Digital I/O 5 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
32
D6
Digital I/O 6 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
33
D7
Digital I/O 7 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
34
D8
Digital Output 8 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
35
D9
Digital Output 9 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
36
D10
Digital Output 10 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
37
D11
Digital Output 11 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
40
EOC
End-of-Conversion Output. EOC goes low to indicate the end of a conversion. It
returns high on the next rising CLK edge or the falling CONVST edge.
41
EOLC
End-of-Last-Conversion Output. EOLC goes low to indicate the end of the
last conversion. It returns high when CONVST goes low for the next
conversion sequence.
42
RD
Read Input. Pulling RD low initiates a read command of the parallel data bus.
43
WR
Write Input. Pulling WR low initiates a write command for configuring the device
with D0–D7.
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