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參數(shù)資料
| 型號： | MAX1304ECM/V+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 4000KSPS 8CH 48LQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 3.65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.82W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
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MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
______________________________________________________________________________________
21
Applications Information
Digital Interface
The bidirectional parallel digital interface allows for setting
the 8-bit configuration register (see the
Configuration
Register section) and reading the 12-bit conversion
result. The interface includes the following control signals:
chip select (CS), read (RD), write (WR), end of conversion
(EOC), end of last conversion (EOLC), conversion start
(CONVST), shutdown (SHDN), channel shutdown
(CHSHDN), internal clock select (INTCLK/EXTCLK), and
external clock input (CLK). Figures 6, 7, 8, 9, Table 2, and
the
Timing Characteristics show the operation of the inter-
face. D0–D7 are bidirectional, and D8–D11 are output
only. D0–D11 go high impedance when RD = 1 or CS = 1.
Configuration Register
Enable channels as active by writing to the configura-
tion register through I/O lines D0–D7 (Table 2). The bits
in the configuration register map directly to the chan-
nels, with D0 controlling channel zero, and D7 control-
ling channel seven. Setting any bit high activates the
corresponding input channel, while resetting any bit
low deactivates the corresponding channel. On the
devices with less than eight channels, some of the bits
have no function (Table 2).
To write to the configuration register, pull CS and WR
low, load bits D0 through D7 onto the parallel bus, and
force WR high. The data are latched on the rising edge
of WR (Figure 6). Write to the configuration register at
any point during the conversion sequence. At power-
up, write to the configuration register to select the
active channels before beginning a conversion.
However, the new configuration does not take effect
until the next CONVST falling edge. At power-up all
channels default active. Shutdown does not change the
configuration register. The configuration register may
be written to in shutdown. See the
Channel Shutdown
(CHSHDN) section for information about using the con-
figuration register for power saving.
Table 2. Configuration Register
BIT/CHANNEL
PART
NUMBER
STATE
D0/CH0
D1/CH1
D2/CH2
D3/CH3
D4/CH4
D5/CH5
D6/CH6
D7/CH7
ON
1
111
11
MAX1304
MAX1308
MAX1312
OFF
0
000
00
ON
1
111X
X
MAX1305
MAX1309
MAX1313
OFF
0
000X
X
ON
1
XX
MAX1306
MAX1310
MAX1314
OFF
0
XX
X = Don’t care (must be 1 or 0).
D0–D7
DATA-IN
RD
CONVST
CONFIGURATION
REGISTER UPDATES
CS
WR
tCS
tWRL
tCTW
tDTW
tWTD
tWTC
Figure 6. Write Timing
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