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參數(shù)資料
| 型號： | MAX1304ECM/V+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 4000KSPS 8CH 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 3.65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.82W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
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MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
20
______________________________________________________________________________________
Data Throughput
The data throughput (fTH) of the MAX1304–MAX1306/
MAX1308–MAX1310/MAX1312–MAX1314 is a function
of the clock speed (fCLK). In internal clock mode, fCLK =
15MHz (typ). In external clock mode, 100kHz
≤ fCLK ≤
20MHz. When reading during conversion (Figures 7 and
8), calculate fTH as follows:
where N is the number of active channels and tQUIET is
the period of bus inactivity before the rising edge of
CONVST. See the
Starting a Conversion section for
more information.
Table 1 uses the above equation and shows the total
throughput as a function of the number of channels
selected for conversion.
Clock Modes
The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314 provide a 15MHz internal conversion clock.
Alternatively, an external clock can be used.
Internal Clock
Internal clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For inter-
nal clock operation, connect INTCLK/EXTCLK to AVDD
and connect CLK to DGND. Note that INTCLK/EXTCLK
is referenced to AVDD, not DVDD.
External Clock
For external clock operation, connect INTCLK/EXTCLK
to AGND and connect an external clock source to CLK.
Note that INTCLK/EXTCLK is referenced to AVDD, not
DVDD. The external clock frequency can be up to
20MHz. Linearity is not guaranteed with clock frequen-
cies below 100kHz due to droop in the T/H circuits.
f
tt
xN
f
TH
ACQ
QUIET
CLK
=
++
+
1
12
3
1
()
Table 1. Throughput vs. Channels Sampled: fCLK = 15MHz, tACQ = 100ns, tQUIET = 50ns
CHANNELS
SAMPLED
(N)
CLOCK CYCLES
UNTIL
LAST RESULT
CLOCK CYCLE
FOR READING
LAST CONVERSION
TOTAL
CONVERSION
TIME (ns)
TOTAL
THROUGHPUT
(ksps)
THROUGHPUT
PER CHANNEL
(fTH)
1
12
1
800
983
2
15
1
1000
1643
821
3
18
1
1200
2117
705
4
21
1
1400
2474
618
5
24
1
1600
2752
550
6
27
1
1800
2975
495
7
30
1
2000
3157
451
8
33
1
2200
3310
413
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| MAX13050ASA-T | 功能描述:CAN 接口集成電路 CAN Transceiver w/80V Fault Protect RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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