參數(shù)資料
型號(hào)： MAS31753FXXXX
廠商： DYNEX SEMICONDUCTOR LTD
元件分類(lèi)： DMA控制器
英文描述： 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84
封裝： QFP-84
文件頁(yè)數(shù)： 30/31頁(yè)
文件大?。?/td> 238K
代理商： MAS31753FXXXX
MA31753
8/31
4.6 DMA MODE / STATUS 1
Mn
0:
Channel n not masked
1:
Channel n masked
EOTn
0:
Channel n “End of Transfer” not reached
1:
Channel n “End of Transfer” reached
Read access only. Value can be changed by writing the channel status register.
ERR
0:
No error detected
1:
Error detected in one or more of the channels
Read access only. Value can be changed by writing the channel status register.
A / B
0:
1750A mode
1:
1750B mode
BP
0:
Even bus parity used
1:
Odd bus parity used
DMAE
0:
DMA requests disabled
1:
DMA requests enabled
Read access only
Pri
000: Channel priority 0, 1, 2, 3, C
001: Channel priority 1, 2, 3, 0, C
010: Channel priority 2, 3, 0, 1, C
011: Channel priority 3, 0, 1, 2, C
100: Channel priority C, 0, 1, 2, 3
101: Channel priority C, 1, 2, 3, 0
110: Channel priority C, 2, 3, 0, 1
111: Channel priority C, 3, 0, 1, 2
5.0 DMA INSTRUCTIONS
60 DMA instructions are present in the memory or IO space between A[7:15] = 0 and A[7:15] = 1DF. Each DMA instruction
comprises of 8 16-bit words. The base address for each instruction is 8*n where n is the instruction number. The instructions are
structured as below:
Words 4, 5 and 6 are used only during area to area mode transfers. Word 6 can only be used for channels 0 and 1.
M3
M2
M1
M0 EOT3 EOT2 EOT1 EOT0 ERR A/B
BP DMAE
Priority
D0
D15
Word numbe r
Cont e nt
0
Mode/Link word
1
Block length
2
Area 1 base address
3
Area 1 PB, PS and AS
4
Area 2 base address
5
Area 2 PB, PS and AS
6
Transfer interval
7
Not used
相關(guān)PDF資料
PDF描述
MAR28155CXXXX 24 I/O, PIA-GENERAL PURPOSE, CDIP40
MAR28155LXXXX 24 I/O, PIA-GENERAL PURPOSE, CQCC44
MAS28155CXXXX 24 I/O, PIA-GENERAL PURPOSE, CDIP40
MAH28155LXXXX 24 I/O, PIA-GENERAL PURPOSE, CQCC44
MAX3100ETG+ 1 CHANNEL(S), 230.4K bps, SERIAL COMM CONTROLLER, QCC24
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