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參數(shù)資料
| 型號(hào)： | MAS31753FXXXX |
| 廠商： | DYNEX SEMICONDUCTOR LTD |
| 元件分類： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84 |
| 封裝： | QFP-84 |
| 文件頁(yè)數(shù)： | 28/31頁(yè) |
| 文件大?。?/td> | 238K |
| 代理商： | MAS31753FXXXX |
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MA31753
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4.0 DETAILED REGISTER DESCRIPTION
The internal registers on the DMA controller can be located
in either memory or IO addressing space. 32 words are control
registers and 480 words are the DMA instruction registers.
The address lines A[7:15] are used to decode the registers.
(A[0:6] are decoded to generate CSN low ie. the user can
place the DMA on the address map.)
4.1 MODE REGISTERS
CA
read 0: channel not active
write 0: stop channel
read 1: channel active
write 1: start channel
This bit will be set low at an error or EOT condition
Mode 000:
Single Word
001:
Double Word
010:
Burst Mode
011:
Not used (channel not started)
100:
Area to Area, Memory to Memory
101:
Area to Area, Memory to IO
110:
Area to Area, IO to Memory
111:
Area to Area, IO to IO
A1M
Area 1 Mode
For single, double and burst modes
00:
Read from memory, incrementing address
01:
Read from memory, decrementing address
10:
Write to memory, incrementing address
11:
Write to memory, decrementing address
Area to area mode
00:
Area 1 address constant
01:
Area 1 address incrementing
10:
Area 1 address decrementing
11:
Area 1 address constant
A2M
Area 2 Mode (only used in area to area mode)
00:
Area 2 address constant
01:
Area 2 address incrementing
10:
Area 2 address decrementing
11:
Area 2 address constant
SEOT 0:
Signal ‘End of Transfer’ at end of current block
only of C=0
1:
Always signal ‘End of Transfer’ at end of
current block.
C
read 0: Perform no chaining
read 1: Perform chaining using the value of “next
Instruction” field as pointer
write 0: Perform no chaining even if defined by current
DMA instruction
write 1: Perform chaining as defined by current
instruction
Next
These 6 bits point to one of the 60 DMA instructions ie.
Inst
the next instruction to be executed.
If the number is 3C, 3D, 3E or 3F, then the transfer will
stop with the current block (ie. no chaining)
A[ 7:15]
Re gister Cont ent
P arit y
0
DMA Instruction
Yes
..
.
..
.
1DF
DMA Instruction
Yes
1E0
Channel 0 Mode
No
1E1
Channel 0 Remaining words
No
1E2
Channel 0 Area 1 current address
No
1E3
Channel 0 Area 1 current PB/AS/PS
No
1E4
Channel 0 Area 2 current address
No
1E5
Channel 0 Area 2 current PB/AS/PS
No
1E6
Channel 0 Status
No
1E7
DMA Mode / Status 1
No
1E8
Channel 1 Mode
No
1E9
Channel 1 Remaining words
No
1EA
Channel 1 Area 1 current address
No
1EB
Channel 1 Area 1 current PB/AS/PS
No
1EC
Channel 1 Area 2 current address
No
1ED
Channel 1 Area 2 current PB/AS/PS
No
1EE
Channel 1 Status
No
1EF
RESERVED
No
1F0
Channel 2 Mode
No
1F1
Channel 2 Remaining words
No
1F2
Channel 2 Area 1 current address
No
1F3
Channel 2 Area 1 current PB/AS/PS
No
1F4
Channel 2 Area 2 current address
No
1F5
Channel 2 Area 2 current PB/AS/PS
No
1F6
Channel 2 Status
No
1F7
RESERVED
No
1F8
Channel 3 Mode
No
1F9
Channel 3 Remaining words
No
1FA
Channel 3 Area 1 current address
No
1FB
Channel 3 Area 1 current PB/AS/PS
No
1FC
Channel 3 Area 2 current address
No
1FD
Channel 3 Area 2 current PB/AS/PS
No
1FE
Channel 3 Status
No
1FF
RESERVED
No
Mode Register
CA
Mode
A1M
A2M
SEOT C
Next Instruction
D0
D15
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