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| 型號： | M8813F3Y-90K1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 73/85頁 |
| 文件大小： | 601K |
| 代理商： | M8813F3Y-90K1 |
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M88 FAMILY
Table 54B. Port A Peripheral Data Mode Write Timing (3 V Range)
Note: 1. RD has the same timing as the DS, LDS, UDS, and PSEN signals.
2. WR has the same timing as the E, DS, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Table 55A. Reset Timing (5 V Range)
Note: 1. RESET will not reset Flash or EEPROM programming/erase cycles.
Table 55B. Reset Timing (3 V Range)
Note: 1. RESET will not reset Flash or EEPROM programming/erase cycles.
Table 56A. VSTBY(ON) Timing (5 V Range)
Note: 1. VSTBY(ON) timing is measured at VCC ramp rate of 2 ms.
Table 56B. VSTBY(ON) Timing (3 V Range)
Symbol
Parameter
Conditio ns
-15
Unit
Min
Max
tWLQV (PA)
WR to Data Propagation Delay
(Note 2)
45
ns
tDVQV (PA)
Data to Port A Data Propagation Delay
(Note 5)
50
ns
tWHQZ (PA)
WR Invalid to Port A Tri-state
(Note 2)
33
ns
Symbol
Parameter
Conditio ns
Min
Max
Unit
tNLNH
RESET Active Low Time
(Note 1)
150
ns
tNLNH(PO)
Power-On-Reset Active Low Time
1
ms
tNLNH(A)
Warm-Reset Active Low Time
25
s
tOPR
RESET High to Operational Device
120
ns
Symbol
Parameter
Conditio ns
Min
Max
Unit
tNLNH
RESET Active Low Time
(Note 1)
300
ns
tNLNH(PO)
Power-On-Reset Active Low Time
ms
tNLNH(A)
Warm-Reset Active Low Time
s
tOPR
RESET High to Operational Device
300
ns
Symbol
Parameter
Conditio ns
Min
Typ
Max
Unit
tBVBH
VSTBY Detection to VSTBY on Output High
20
s
tBXBL
VSTBY Off Detection to VSTBY on Output
Low
20
s
Symbol
Parameter
Conditio ns
Min
Typ
Max
Unit
tBVBH
VSTBY Detection to VSTBY(ON) Output High
2.0
s
tBXBL
VSTBY Off Detection to VSTBY(ON) Output
Low
2.0
s
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