
M88 FAMILY
66/85
Table 50A. Read Timing (5 V Range)
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal M88x3Fxx FLASH+P SD function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
Symbol
Parameter
Condi tions
-90
-15
Turbo
Off
Unit
Min
Max
Min
Max
tLVLX
ALE or AS Pulse Width
20
28
ns
tAVLX
Address Setup Time
(Note 3)
610
ns
tLXAX
Address Hold Time
(Note 3)
811
ns
tAVQV
Address Valid to Data Valid
(Note 3)
90
150
Add 10
ns
tSLQV
CS Valid to Data Valid
100
150
ns
tRLQV
RD to Data Valid 8-Bit Bus
(Note 5)
32
40
ns
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251
(Note 2)
38
45
ns
tRHQX
RD Data Hold Time
(Note 1)
00
ns
tRLRH
RD Pulse Width
(Note 1)
32
38
ns
tRHQZ
RD to Data High-Z
(Note 1)
25
30
ns
tEHEL
E Pulse Width
32
38
ns
tTHEH
R/W Setup Time to Enable
10
18
ns
tELTL
R/W Hold Time After Enable
0
ns
tAVPV
Address Input Valid to
Address Output Delay
(Note 4)
25
32
ns