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參數(shù)資料
| 型號： | M8813F3Y-90K1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 35/85頁 |
| 文件大?。?/td> | 601K |
| 代理商： | M8813F3Y-90K1 |
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M88 FAMILY
40/85
Table 22. Port Operating Modes
Note: 1. Can be multiplexed with other I/O functions.
Table 23. Port Operating Mode Settings
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B, C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND array.
3. Any of these three methods will enable JTAG pins on Port C.
Port Mode
Port A
Port B
Port C
Port D
MCU I/O
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Address Out
Yes (A7 – 0)
or (A15 – 8)
No
Address In
Yes
Data Port
Yes (D7 – 0)
No
Peripheral I/O
Yes
No
JTAG ISP
No
Yes1
No
Mode
Defined In
PSDabel
Defined In
PSDconfiguratio n
Control
Register
Setting
Direction
Register
Setting
VM
Register
Setting
JTAG Enable
MCU I/O
Declare pins only
N/A1
0
1 = output,
0 = input
(Note 2)
N/A
PLD I/O
Logic equations
N/A
(Note 2)
N/A
Data Port (Port A)
N/A
Specify bus type
N/A
Address Out
(Port A,B)
Declare pins only
N/A
1
1 (Note 2)
N/A
Address In
(Port A,B,C,D)
Logic for equation
Input Macrocells
N/A
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
N/A
PIO bit = 1
N/A
JTAG ISP (Note 3)
JTAGSEL
JTAG
Configuration
N/A
JTAG_Enable
As shown in Figure 27, the ports contain an output
multiplexer whose selects are driven by the
configuration bits in the Control Registers (Ports A
and B only) and PSDsoft Configuration. Inputs to
the multiplexer include the following:
t Output data from the Data Out Register
t Latched address outputs
t CPLD Macrocell output
t External Chip Select from CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
PDB is connected to the Internal Data Bus for
feedback and can be read by the microcontroller.
The Data Out and Macrocell outputs, Direction
and Control Registers, and port pin input are all
connected to the PDB.
The Port pin’s tri-state output driver enable is
controlled by a two input OR gate whose inputs
come from the CPLD AND array enable product
term and the Direction Register. If the enable
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| M8803F3Y-90K1T | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
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