參數(shù)資料
型號(hào)： M8813F3Y-90K1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 22/85頁(yè)
文件大?。?/td> 601K
代理商： M8813F3Y-90K1
29/85
M88 FAMILY
Table 18. Output Macrocell Port and Data Bit Assignments
Output
Macrocell
Port
Assignment
Native Product Terms
Maximum Borrowed
Product Terms
Data Bit for Loading or
Reading
McellAB0
Port A0, B0
3
6
D0
McellAB1
Port A1, B1
3
6
D1
McellAB2
Port A2, B2
3
6
D2
McellAB3
Port A3, B3
3
6
D3
McellAB4
Port A4, B4
3
6
D4
McellAB5
Port A5, B5
3
6
D5
McellAB6
Port A6, B6
3
6
D6
McellAB7
Port A7, B7
3
6
D7
McellBC0
Port B0, C0
4
5
D0
McellBC1
Port B1, C1
4
5
D1
McellBC2
Port B2, C2
4
5
D2
McellBC3
Port B3, C3
4
5
D3
McellBC4
Port B4, C4
4
6
D4
McellBC5
Port B5, C5
4
6
D5
McellBC6
Port B6, C6
4
6
D6
McellBC7
Port B7, C7
4
6
D7
Each of the blocks are described in the sections
that follow.
The Input and Output Macrocells are connected to
the M88x3Fxx FLASH+PSD internal data bus and
can be directly accessed by the microcontroller.
This enables the MCU software to load data into
the Output Macrocells or read data from both the
Input and Output Macrocells.
This feature allows efficient implementation of
system logic and eliminates the need to connect
the data bus to the AND logic array as required in
most standard PLD macrocell architectures.
Output Macrocell
Eight of the Output Macrocells are connected to
Ports A and B pins and are named as McellAB0-7.
The other eight Macrocells are connected to Ports
B and C pins and are named as McellBC0-7. If an
McellAB output is not assigned to a specific pin in
PSDabel, the Macrocell Allocator will assign it to
either Port A or B. The same is true for a McellBC
output on Port B or C. Table 18 shows the
Macrocells and Port assignment.
The Output Macrocell (OMC) architecture is
shown in Figure 17. As shown in the figure, there
are native product terms available from the AND
array, and borrowed product terms available (if
unused) from other OMCs. The polarity of the
product term is controlled by the XOR gate. The
OMC can implement either sequential logic, using
the flip-flop element, or combinatorial logic. The
multiplexer selects between the sequential or
combinatorial logic outputs. The multiplexer output
can drive a Port pin and has a feedback path to the
AND array inputs.
The flip-flop in the OMC can be configured as a D,
T, JK, or SR type in the PSDabel program. The
flip-flop’s clock, preset, and clear inputs may be
driven from a product term of the AND array.
Alternatively, the external CLKIN signal can be
used for the clock input to the flip-flop. The flip-flop
is clocked on the rising edge of the clock input.
The preset and clear are active-high inputs. Each
clear input can use up to two product terms.
The Product Term Allocator
The CPLD has a Product Term Allocator. The
PSDabel compiler, in PSDsoft, uses the Allocator
to borrow and place product terms from one
Macrocell
to
another.
The
following
list
summarizes how product terms are allocated:
s
McellAB0-7 all have three native product terms
and may borrow up to six more
s
McellBC0-3 all have four native product terms
and may borrow up to five more
相關(guān)PDF資料
PDF描述
M8813F3Y-90T1 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
M8803F3Y-90K1T 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
M8813F3Y-90K1T 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
M906-01-125.0000LF 125 MHz, OTHER CLOCK GENERATOR, CQCC36
M906-01-125.0000LF 125 MHz, OTHER CLOCK GENERATOR, CQCC36
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