
M65761FP
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 14 of 33
(8) Number of lines to be processed specified (R)
(Address: 8)
d7
d0
LIN_REG_L:
LINE_L
(Address: 9)
LIN_REG_H:
LINE_H
d0 to 7 (LINE_L):
The number of lines actually processed is read out (Lower bytes) (0 to 65535)
d0 to 7 (LINE_H):
The number of lines actually processed is read out (Upper bytes)
When the number of lines processed number of lines set, coding/decoding/through stops
temporarily/end of processing.
Note:
The number of lines to be processed by this processing is cleared to 0 by the issuance of
process start command.
(9) Data write in buffer (W) (See note 1)
(Address: A)
d7
d0
DWR_BUF_L:
DWR_L
(Address: B)
DWR_BUF_H:
DWR_H
d0 to 7 (DWR_L):
This writes in the coded data/image data/context table RAM data (Lower bytes)
d0 to 7 (DWR_H):
This writes in the coded data/image data/context table RAM data (Upper bytes)
(10) Data read out buffer (R) (See note 1)
(Address: A)
d7
d0
DRD_BUF_L:
DRD_L
(Address: B)
DRD_BUF_H:
DRD_H
d0 to 7 (DRD_L):
This read out the coded data/image data/context table RAM data. (Lower bytes)
d0 to 7 (DRD_H):
This read out the coded data/image data/context table RAM data. (Upper bytes)
Note:
1. Address A is used with 8-bit bus. In case of the 16-bit bus, only the word access is possible. (Not byte
access) If the number of coded data bytes is an odd number during coding, an one byte pad ("00") is
attached after the end marker is issued in order to use it as a word boundary.
See table 1 for the bit arrangement used during the coded data/image data. In case of the context table RAM
data, only the lower byte becomes valid data regardless of the bus width of the host bus (BUS16).
Table 3 Context Data Lineup
Upper Address (B)
Lower Address (A)
Host I/F
Bus Width
d15
d8
d7
d6
d0
8-bit
—
mps
s6
s0
16-bit
-—
mps
s6
s0
Note:
mps: Superior symbol MPS (expected value 0/1)
s6 to 0: Status number ST (0 to 112)