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參數(shù)資料
| 型號： | M65761FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 7/36頁 |
| 文件大?。?/td> | 297K |
| 代理商： | M65761FP |
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M65761FP
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 13 of 33
d3 (SE):
SC count over error interrupt during coding. (0: interrupt mask, 1: interrupt enable)
This bit sets to 1 beforehand, it occurs the interruption when the SC counter is overflow during coding.
Processing of coding continues, but the correct coded data is not output.
Note:
Bits, d0 to d3, are for interrupt enable of bits d0 to d2 and d4 of the status register.
The interrupt request signal (INTR) is asserted when any one of the status bit set in the interrupt
enable (D0 (JE) generates interrupts even during the temporary stop), the status goes to "0" due to
H/W reset or the INTR signal is negated when the interrupt mask causes factors for interrupt to be
lost. Moreover, the status register will not be cleared by the generation of interrupts or the R/W of
the interrupt enable register.
d7 (MP):
This specified the marker code detection time halt. (0: continue/restart, 1: temporary halt)
Decoding will stop temporarily when the marker code is detected if this MP bit is preset to "1" during
decoding. (It occurs interruption when the marker code is detected, if the ME bit preset to "1".)
If decoding is not completed during the temporary halt, it is possible to reset the line number setup register.
Next, if this MP bit is set to "0", decoding is restarted. (Decoding continues to the line number set.)
(6) Register used to set the number of pixels (W/R)
(Address: 4)
d7
d0
PEL_REG_L:
PEL_L
(Address: 5)
d7
d5
d0
PEL_REG_H:
0
PEL_H
d0 to 7 (PEL_L):
Number of pixels/line is set (Lower byte)
d0 to 5 (PEL_H):
Number of pixels/line is set (Upper byte)
It is possible to set up 8192 pixels maximum when 3-line template is used. It is used to set up
10240 pixels maximum when 2-line template is used. The number of pixels actually coded (or
decoded) should be set when reducing (or expanding). When the image bus uses 16 bits (or 32 bits)
in parallel I/F, multiples of 16 (or 32) should be set. In case of serial I/F, multiples of 8 should be
used.
(7) Line number setting register (W/R)
(Address: 6)
d7
d0
LSET_REG_L:
LSET_L
(Address: 7)
LSET_REG_H:
LSET_H
d0 to 7 (LSET_L):
This sets the number of lines to be processed. (Lower bytes)
(1 to 65535, 0 line not used)
d0 to 7 (LSET_H):
This sets the number of lines to be processed. (Upper bytes)
When reducing (magnification) the actual number of lines to be coded (decoded) should be set.
The number of lines (relative number of lines) from the process start command to be issued from
now the immediately following temporary stop/end of trailer should be set. This register should
be set to the value specified before the process star command is issued. Moreover, this register
can be rewritten during processing as long as the following conditions are met:
If the maximum value, (65535), is set before the process start command is issued, it can be
reset once during processing.
If a value other than maximum value (65535) is set before the process start command is
issued and if resetting becomes necessary during processing, the maximum value (65535) has
to be reset once and desired value should the reset.
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相關(guān)代理商/技術(shù)參數(shù) |
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