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參數(shù)資料
| 型號： | M65761FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 6/36頁 |
| 文件大小： | 297K |
| 代理商： | M65761FP |
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M65761FP
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 12 of 33
d2 (RC):
This command starts and stops R/W of context table RAM. (1: R/W start, 0: R/W end)
The context table RAM is read out or written in by making this bit to "1".
When reading/writing is finished, this bit must have "0" on it.
d3 (JP):
This selected temporary stop and the end of termination of coding/decoding/through processing.
(1: Temporary stop selected, 0: End of processing selected)
When the process start command d1 (JC) is issued by making this JP bit to 1, the processing stops
temporarily when the set number of lines have been processed. Then, if the process start command d1 (JC)
is issued, processing restarts. (See " Sequence of Setting Up Registers " (3))
(4) Status register (R)
(Address: 2)
d7
d5
d0
STAT_REG:
0
PS
SC
IS
MS
DS
JS
d0 (JS):
This register indicates the status of processing in initialization, coding, decoding and through.
(0: Processing in progress (being initialized), 1: End of processing)
This JS bit goes to "1" when the initialization is completed as RAM initialization command is issued.
(IC = 1) This JS bit goes to "1" when all coded data has been read out during coding in case when the
process start command of the processing end is issued. (JC = 1, JP = 0) This JS bit goes to "1" when
reading all the image data has been completed during the image data through and decoding. Moreover, this
JS bit stays "0" even when the set number of lines have been processed when the command to start
processing the process which has been stopped temporarily has been issued (JC = 1, JP = 1). (However,
interrupts are issued during the temporary stops.)
d1 (DS):
This is used for read and write ready of coded data. (In case of the through mode, this is used for the image
data.) (1: Ready, 0: Reading no possible)
It is possible to do R/W of data by the way of the data write/read buffer when this bit is 1.
d2 (MS):
This detects the marker code during decoding. (0: not detected, 1: detected)
This bit goes to "1" if any marker is detected during decoding.
d3 (IS):
This indicates the status of the interrupt request. (0: No request, 1: Request exists)
d4 (SC):
This shows the SC count over error during coding. (0: Normal, 1: There is a SC counter overflow)
Note:
The SC counter counts the "FF" data bytes which occur during coding. Coding continues even
when the SC counter overflows, this means correct coding data will not be outputted. (Coding error)
d5 (PS):
Processing modes (Stopped temporary/End of trailer) (1: Process temporarily stopped, 0: End of processing)
This PS bit corresponds to the temporary stop and end of processing of d3 bit (JP) processing of the
command register.
(5) Interrupt enable register (W/R)
(Address: 3)
d7
d3
d0
IENB_REG
MP
0
SE
ME
DE
JE
d0 (JE):
Temporary stop/end of trailer interrupt of initialization/coding/decoding/through.
(0: interrupt mask, 1: interrupt enable)
d1 (DE):
Coded data (image data) read out/write in ready interrupt.
(0: interrupt mask, 1: interrupt enable)
d2 (ME):
Marker code detection interrupt during decoding. (0: interrupt mask, 1: interrupt enable)
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相關(guān)代理商/技術(shù)參數(shù) |
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