Reset
25
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Figure 1.5.6. VCR1 Register, VCR2 Register, and D4INT Register
VC13
Power supply detection register 1
b7
b
3
0 0 0 0
0 0 0
Symbol
VCR1
Address
0019
16
After reset (Note 2)
00001000
2
Power supply down monitor
flag (Note 1)
Reserved bit
Bit name
Function
Bit symbol
RW
b
b4
b
b
b1
b
0
Note 1: The VC13 bit is useful when the VC27 bit of VCR2 register is set to “1” (power supply down detection circuit
enable). The VC13 bit is always “1” (V
CC1
4 V) when the VC27 bit in the VCR2 register is set to “0” (power
supply down detection circuit disable).
Note 2: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
0:V
CC1
< Vdet4
1:V
CC1
Vdet4
Must set to “0”
RO
RW
RW
Reserved bit
Must set to “0”
Power supply detection register 2 (Note 1)
Symbol
VCR2
Address
001A
16
After reset (Note 6)
00
16
Bit name
Bit symbol
b7
b
6
b
5
b4
0 0 0 0 0
b
b
b1
b
0
Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: To use hardware reset 2, set the VC26 bit to “1” (reset level detection circuit enable).
Note 3: To use hardware reset 2 in stop mode, set the VC25 bit to “1” (RAM retention limit detection circuit enable).
VC26 bit is disabled in stop mode. (The microcomputer is not reset even if the voltage input to Vcc
1
pin
becomes lower than Vdet3.)
Note 4: To use the WDC5 bit in the WDC register, set the VC25 bit to “1” (RAM retention limit detection circuit enable).
Note 5: Where the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to “1”
(power supply down detection interrupt enable), set the VC27 bit to “1” (power supply down detection circuit
enable).
Note 6: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 7: The detection circuit does not start operation until td(E-A) elapses after the VC25 bit, VC26 bit, or VC27 bit is
set to “1”.
VC25
RAM retention limit
detection monitor bit
(Notes 3, 4, 7)
0: Disable RAM retention limit
detection circuit
1: Enable RAM retention limit
detection circuit
0: Disable reset level detection
circuit
1: Enable reset level detection
circuit
0: Disable power supply down
detection circuit
1: Enable power supply down
detection circuit
VC26
VC27
RW
RW
RW
RW
RW
Function
Reserved bit
Must set to “0”
Reset level monitor bit
(Notes 2, 3, 7)
Power supply down monitor
bit (Note 5)
(b2-b0)
(b7-b4)
(b4-b0)
D40
Power supply down detection interrupt register (Note 1)
Symbol
D4INT
Address
001F
16
After reset
00
16
Power supply down detection
interrupt enable bit (Note 5)
STOP mode deactivation
control bit
(Note 4)
Bit name
Bit symbol
b7 b6
b5
b4
b3
b2
b1 b0
0 :
Disable
1 :
Enable
D41
0: Disable (do not use the power
interrupt to get out of stop mode)
1: Enable (use the power supply
out of stop mode)
D42
Power supply change
detection flag (Note 2)
0: Not detected
1: Vdet4 passing detection
D43
WDT overflow detect flag
0: Not detected
1: Detected
DF0
Sampling clock select bit
00 : CPU clock divided by 8
01 : CPU clock divided by 16
11 : CPU clock divided by 64
DF1
Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: Useful when the VC27 bit in the VCR2 register is set to “1” (power supply down detection circuit enabled).
If the VC27 bit is set to “0” (power supply down detection circuit disable), the D42 bit is set to “0” (Not
detect).
Note 3: This bit is set to “0” by writing a “0” in a program. (Writing a “1” has no effect.)
Note 4: If the power supply down detection interrupt needs to be used to get out of stop mode again after once
used for that purpose, reset the D41 bit by writing a “0” and then a “1”.
Note 5: The D40 bit is useful where the VC27 bit in the VCR2 register is set to “1”.
b5b4
RW
RW
RW
(Note 3)
RW
(Note 3)
RW
RW
(b7-b6)
Function
Nothing is assigned. When write, set to “0”. When read, its
content is “0”.