參數(shù)資料
型號(hào): M5M4V64S40ATP-10L
廠商: Mitsubishi Electric Corporation
英文描述: 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
中文描述: 64M號(hào)(4銀行甲1048576字x 16位)同步DRAM
文件頁數(shù): 22/51頁
文件大?。?/td> 1084K
代理商: M5M4V64S40ATP-10L
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed.
WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=4)
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ
cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
DQ
Write
Yi
0
00
Write
Yk
0
10
Dai0
Daj0
Daj1
Dbk0
Write
Yj
0
00
Dbk1 Dbk2
Write
Yl
0
00
Dal0
Dal1
Dal2
Dal3
A11
CLK
Command
A0-9
A10
BA0,1
DQ
Write
Yi
0
00
Qaj0
READ
Yj
0
00
Qaj1
Dai0
Dbk0 Dbk1
DQM
Write
Yk
0
10
READ
Yl
0
00
Qal0
A11
22
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