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參數(shù)資料
| 型號(hào)： | M5M4V16169DTP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| 中文描述： | 16MCDRAM：16米（100萬字由16位）與16K的緩存內(nèi)存（1024字由16位）的SRAM |
| 文件頁數(shù)： | 4/64頁 |
| 文件大?。?/td> | 737K |
| 代理商： | M5M4V16169DTP |
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
H
H
X
X
X
X
X
X
X
NOP
H
CS#
CMs#
CAS#
DQC
(u/l)
WE#
CC0# CC1#
Mnemonic
CODE
Previous
RAS#
DTD#
Ad2
DRAM
Ad
(
DRAM address
)
Ad1
Ad0-11
As
SRAM
(SRAM
As0-9
Previous
CMd#
Ad0
X
X
4
X
X
X
X
X
X
X
X
X
X
SPD
L
X
X
L
X
X
X
X
X
X
X
H
H
DES
H
X
SR
L
X
X
X
X
As0-9
H
H
H
L
H
X
L
X
X
X
X
As0-2
H
H
L
L
BR
H
X
L
X
X
X
X
As0-2
H
L
L
L
BW
H
X
L
X
X
X
X
As0-9
H
L
H
L
SW
H
X
L
X
X
X
X
As3-9
L
H
L
H
BRT
H
X
BWT
L
X
X
X
X
As3-9
L
L
L
H
H
X
L
X
X
X
X
As0-9
H
H
L
H
BRTR
H
X
BWTW
L
X
X
X
X
As0-9
H
L
L
H
H
X
DPD
X
X
X
X
X
X
X
X
X
X
L
L
H
H
X
X
X
X
X
X
X
DNOP
X
H
DRT
L
H
L
H
Ad3-7
(Col.Block)
X
X
X
X
X
X
H
0
0
0
L
H
L
L
0
0
Ad3-7
(Col.Block)
X
X
X
X
X
DWT1
X
H
0
L
0
0
H
L
L
Ad3-7
(Col.Block)
X
X
X
X
X
DWT1R
X
H
1
L
0
1
Ad3-7
(Col.Block)
Ad3-7
(Col.Block)
H
L
L
X
X
X
X
X
DWT2
X
H
0
L
0
1
H
L
L
X
X
X
X
X
DWT2R
X
H
1
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
L
L
L
H
X
X
X
X
X
X
ARF
X
H
L
L
L
L
Command
X
X
X
X
X
SCR
X
H
L
L
H
L
X
X
X
X
X
X
PCG
X
H
L
L
H
H
Ad0-11
(Row Add.)
X
X
X
X
X
ACT
X
H
L
L
L
H
X
X
X
X
X
X
SRF
X
H
(7)
(8)
NOTES
1) For the DPD function, the RAS#, CAS# and DTD# inputs are
DON'T CARE except for the L,L,H combination. (Respectively).
2) The unused addresses must be set to Low.
3) Use New: If BW or BWT or BWTW is initiated the same cycle
as DWT1 or DWT1R, new data is loaded into the buffer
and transferred to DRAM.
4) Clear 1 or 2 Transfer Mask Bits (as addressed by As0-2 and DQCU/L).
5) Actual number of bits transfer depends on the state of the DTBW Mask and
the DQCU/DQCL inputs. Note: If DQC(U/L) is Low, the corresponding DQ(s)
is(are) disabled (Input and Output Buffer). SR,SW,BR and BW cycles
with DQCU and DQCL Low result in a Deselect SRAM operation.
6) Following a DWT1 or DWT1R cycle, the entire WB1 Transfer Mask is Set .
(i.e. , data can no longer be transferred from WB1 to DRAM.)
Succeeding Buffer-Writes or Buffer Write Transfers will Clear Mask bits.
7) CMd# during current cycle must be High (see timing diagram for Auto-Refresh).
8) CMd# during current cycle must be Low (see timing diagram for Self-Refresh).
L
X
X
X
X
H
L
H
H
X
LBM
H
X
L
H
L
L
1
0
Ad3-7
(Col.Block)
X
X
X
X
X
DWT3
X
H
0
L
1
0
H
L
L
Ad3-7
(Col.Block)
Ad3-7
(Col.Block)
X
X
X
X
X
DWT3R
X
H
1
L
1
1
H
L
L
X
X
X
X
X
DWT4
X
H
0
L
1
1
Ad3-7
(Col.Block)
H
L
L
X
X
X
X
X
DWT4R
X
H
1
(2)
(2)
(2)
(2)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V16169DTP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16G50DFP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
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