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參數(shù)資料
| 型號： | M5M4V16169DTP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| 中文描述： | 16MCDRAM：16米（100萬字由16位）與16K的緩存內(nèi)存（1024字由16位）的SRAM |
| 文件頁數(shù)： | 14/64頁 |
| 文件大?。?/td> | 737K |
| 代理商： | M5M4V16169DTP |
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (7)
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
DRAM Write
Transfer2
DRAM Write
Transfer2
& Read
Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3-
Ad7. Addresses Ad8-Ad11 must be set to Low. The WB2 Mask controls the data written to
the DRAM. With the DWT2 function, the WB2 data and WB2 transfer mask remain unchanged.
(Note 4)
Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3-
Ad7. Addresses Ad8-Ad11 must be set to Low. The WB2 transfer mask controls the data
written to the DRAM. With the DWT2 function, the WB2 data and WB2 transfer mask remain
unchanged. The block to which the data is written in DRAM is simultaneously transferred to the
Read Buffer1 and 2. (Notes 1,2,4)
14
DQs
8X16
8X16
8X16
8X16
8X16
16bits
16bits
As3-9
1of128Decode
1of4096Decode
Ad3-7
1of32
Decode
As0-2
1of8
Decode
As0-2
1of8Decode
8X16Block
8X16Block
WB1
Upper Byte
Lower Byte
DRAM RowDecoder
16bits
As0-2
1of8Decode
Upper Byte
Lower Byte
RB2
Upper Byte
Lower Byte
Upper Byte
Lower Byte
RB1
Ad0-11
X
DQs
8X16
8X16
8X16
8X16
16bits
16bits
As3-9
1of128Decode
1of4096Decode
Ad3-7
1of32
Decode
As0-2
1of8
Decode
As0-2
1of8Decode
8X16Block
8X16Block
WB1
WB2
Upper Byte
Lower Byte
DRAM RowDecoder
16bits
As0-2
1of8Decode
Upper Byte
Lower Byte
RB2
Upper Byte
Lower Byte
Upper Byte
Lower Byte
RB1
Ad0-11
X
WB2
SRAM RowDecoder
DRAM
1M X 16
SRAM
1KX16
16bits
SRAM
1KX16
DRAM
1MX16
8X16
16bits
SRAM RowDecoder
DQ8-15
DQ0-7
DQ8-15
DQ0-7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M5M4V16169DRT-10 | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DRT-15 | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DRT-7 | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DRT-8 | 22182053 |
| M5M4V16G50DFP-10 | 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V16169DTP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16G50DFP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
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