參數(shù)資料
型號: M58LW064C110N1T
廠商: 意法半導(dǎo)體
英文描述: 64 Mbit (4Mb x16, Uniform Block, Burst) 3V Supply Flash Memory
中文描述: 64兆位(4Mb的x16插槽,統(tǒng)一座,突發(fā))3V電源快閃記憶體
文件頁數(shù): 29/53頁
文件大?。?/td> 319K
代理商: M58LW064C110N1T
29/53
M58LW064A, M58LW064B
Table 23. Asynchronous Random Read
(T
A
= 0 to 70
°
C, –40 to 85
°
C, V
DD
= 2.7V to 3.6V, V
DDQ
= 1.8V to V
DD
)
Symbol
Parameter
Note: 1. Output Enable G may be delayed up to t
ELQV
- t
GLQV
after the falling edge of Chip Enable E without increasing t
ELQV
.
Test Condition
Min
Max
Unit
t
AVAV
Address Valid to Address Valid
E = V
IL
, G = V
IL
150
ns
t
AVQV
Addrss Valid to Output Valid
E = V
IL
, G = V
IL
150
ns
t
AXQX
Address Transition to Output Transition
E = V
IL
, G = V
IL
0
ns
t
EHLX
Chip Enable High to Latch Enable Transition
0
ns
t
EHQX
Chip Enable High to Output Transition
G = V
IL
0
ns
t
EHQZ
Chip Enable High to Output Hi-Z
G = V
IL
10
ns
t
ELQV(1)
Chip Enable Low toOutput Valid
G = V
IL
150
ns
t
ELQX
Chip Enable Low toOutput Transition
G = V
IL
0
ns
t
GHQX
Output Enable High to Output Transition
E = V
IL
0
ns
t
GHQZ
Output Enable High to Output Hi-Z
E = V
IL
10
ns
t
GLQV
Output Enable Low to Output Valid
E = V
IL
50
ns
t
GLQX
Output Enable to Output Transition
E = V
IL
0
ns
t
LLEL
Latch Enable Low to Chip Enable Low
10
ns
Figure 9. Asynchronous Random Read AC Waveforms
Asynchronous Read (M15 = 1), Random (M3 = 0)
AI03250
E
G
L
A1-A22
(1)
DQ0-DQx
(2)
VALID
tLLEL
tAXQX
tELQV
tELQX
tAVQV
tGLQX
tGLQV
tEHQZ
tEHQX
tEHLX
tGHQX
tGHQZ
See also Page Read
(1)
A1 is not used (Don’t Care) in x32
organization
(2)
DQ0-DQ15 in x16 or DQ0-DQ31 in x32 organization
OUTPUT
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