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| 型號： | M50LPW116N5T |
| 廠商： | 意法半導體 |
| 英文描述： | 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 16兆位的2Mb × 8，啟動塊3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 259K |
| 代理商： | M50LPW116N5T |
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M50LPW116
4/36
Table 2. Memory Identification Input Configuration
Memory
Number
ID3
ID2
ID1
ID0
A25
A24
A23
A21
1 (Boot)
V
IL
or floating
V
IL
or floating
V
IL
or floating
V
IL
or floating
1
1
1
1
2
V
IL
or floating
V
IL
or floating
V
IL
or floating
V
IH
1
1
1
0
3
V
IL
or floating
V
IL
or floating
V
IH
V
IL
or floating
1
1
0
1
4
V
IL
or floating
V
IL
or floating
V
IH
V
IH
1
1
0
0
5
V
IL
or floating
V
IH
V
IL
or floating
V
IL
or floating
1
0
1
1
6
V
IL
or floating
V
IH
V
IL
or floating
V
IH
1
0
1
0
7
V
IL
or floating
V
IH
V
IH
V
IL
or floating
1
0
0
1
8
V
IL
or floating
V
IH
V
IH
V
IH
1
0
0
0
9
V
IH
V
IL
or floating
V
IL
or floating
V
IL
or floating
0
1
1
1
10
V
IH
V
IL
or floating
V
IL
or floating
V
IH
0
1
1
0
11
V
IH
V
IL
or floating
V
IH
V
IL
or floating
0
1
0
1
12
V
IH
V
IL
or floating
V
IH
V
IH
0
1
0
0
13
V
IH
V
IH
V
IL
or floating
V
IL
or floating
0
0
1
1
14
V
IH
V
IH
V
IL
or floating
V
IH
0
0
1
0
15
V
IH
V
IH
V
IH
V
IL
or floating
0
0
0
1
16
V
IH
V
IH
V
IH
V
IH
0
0
0
0
Interface Configuration (IC).
The Interface Con-
figuration input selects whether the Low Pin Count
(LPC) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Low Pin Count (LPC) Interface the
Interface Configuration pin should be left to float or
driven Low, V
IL
; to select the Address/Address
Multiplexed (A/A Mux) Interface the pin should be
driven High, V
IH
. An internal pull-down resistor is
included with a value of R
IL
; there will be a leakage
current of I
LI2
through each pin when pulled to V
IH
;
see Table 20.
Interface Reset (RP).
The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, V
IL
, the memory is in Reset
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, V
IH
, the memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT).
The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK).
The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, LAD0-LAD3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL).
The Top Block Lock
input is used to prevent the Top Block (Block 49)
from being changed. When Top Block Lock, TBL,
is set Low, V
IL
, Program and Block Erase
operations in the Top Block have no effect,
regardless of the state of the Lock Register. When
Top Block Lock, TBL, is set High, V
IH
, the
protection of the Block is determined by the Lock
Register. The state of Top Block Lock, TBL, does
not affect the protection of the other Blocks
(Blocks 0 to 48).
Top Block Lock, TBL, must be set prior to a Pro-
gram or Block Erase operation is initiated and
must not be changed until the operation completes
or unpredictable results may occur. Care should
be taken to avoid unpredictable behavior by
changing TBL during Program or Erase Suspend.
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