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參數(shù)資料
| 型號： | M50LPW116N5T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 16兆位的2Mb × 8，啟動塊3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 1/36頁 |
| 文件大小： | 259K |
| 代理商： | M50LPW116N5T |
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PRELIMINARY DATA
February 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M50LPW116
16 Mbit (2Mb x8, Boot Block)
3V Supply Low Pin Count Flash Memory
I
SUPPLY VOLTAGE
– V
CC
= 3V to 3.6V for Program, Erase and
Read Operations
– V
PP
= 12V for Fast Program and Fast Erase
I
TWO INTERFACES
– Low Pin Count (LPC) Standard Interface for
embedded operation with PC Chipsets.
– Address/Address Multiplexed (A/A Mux) In-
terface for programming equipment compati-
bility.
I
LOW PIN COUNT (LPC) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface supporting
Read and Write Operations
– Hardware Write Protect Pins for Block Pro-
tection
– Register Based Read and Write Protection
– 5 Additional General Purpose Inputs for plat-
form design flexibility
– Synchronized with 33 MHz PCI clock
I
BYTE PROGRAMMING TIME
– Single Byte Mode: 10μs (typical)
– Quadruple Byte Mode: 2.5μs (typical)
I
50 MEMORY BLOCKS
– 1 Boot Block
– 18 Parameter and 31 Main Blocks
I
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program and Block/Chip
Erase algorithms
– Status Register Bits
I
PROGRAM and ERASE SUSPEND
I
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 30h
Figure 1. Logic Diagram (LPC Interface)
AI05466
4
LFRAME
LAD0-
LAD3
VCC
M50LPW116
CLK
VSS
4
IC
RP
TBL
5
INIT
WP
ID0-ID3
GPI0-
GPI4
VPP
TSOP40 (N)
10 x 20mm
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