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參數(shù)資料
| 型號(hào)： | M50LPW116N1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 16兆位的2Mb × 8，啟動(dòng)塊3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 259K |
| 代理商： | M50LPW116N1T |
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M50LPW116
8/36
Table 6. LPC Bus Read Field Definitions
Clock Cycle
Number
Clock
Cycle
Count
Field
LAD0-
LAD3
Memory
I/O
Description
1
1
START
0000b
I
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a
LPC cycle.
2
1
CYCTYPE
+ DIR
0100b
I
Indicates the type of cycle and selects 1-byte reading. Bits
3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b
for read. Bit 0 is reset to 0.
3-10
8
ADDR
XXXX
I
A 32-bit address phase is transferred starting with the
most significant nibble first. A26-A31 must be set to 1. A22
= 1 for Array, A22 = 0 for registers access. For A21, A23-
A25 values, refers to Table 2.
11
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
12
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-LAD3
during this cycle.
13-14
2
WSYNC
0101b
O
The LPC Flash Memory drives LAD0-LAD3 to 0101b
(short wait-sync) for two clock cycles, indicating that the
data is not yet available. Two wait-states are always
included.
15
1
RSYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating that data will be available during the next clock
cycle.
16-17
2
DATA
XXXX
O
Data transfer is two CLK cycles, starting with the least
significant nibble.
18
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
19
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs, the host takes
control of LAD0-LAD3.
Figure 4. LPC Bus Read Waveforms
AI04429
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
CYCTYPE
+ DIR
ADDR
TAR
SYNC
DATA
TAR
1
1
8
2
3
2
2
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