參數(shù)資料
型號: M50LPW116N1T
廠商: 意法半導(dǎo)體
英文描述: 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory
中文描述: 16兆位的2Mb × 8,啟動塊3V電源低引腳數(shù)快閃記憶體
文件頁數(shù): 17/36頁
文件大?。?/td> 259K
代理商: M50LPW116N1T
17/36
M50LPW116
Table 15. Lock Register Bit Definitions
(1)
Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-34] Lock
Register (T_MINUS34_LK).
Table 16. General Purpose Input Register Definition
(1)
Note: 1. Applies to the General Purpose Input Register (GPI_REG).
Bit
Bit Name
Value
Function
7-3
Reserved
2
Read-Lock
‘1’
Bus Read operations in this Block always return 00h.
‘0’
Bus read operations in this Block return the Memory Array contents. (Default
value).
1
Lock-Down
‘1’
Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a
‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset
to ‘0’ following a Reset (using RP or INIT) or after power-up.
‘0’
Read-Lock and Write-Lock can be changed by writing new values to them. (Default
value).
0
Write-Lock
‘1’
Program and Block Erase operations in this Block will set an error in the Status
Register. The memory contents will not be changed. (Default value).
‘0’
Program and Block Erase operations in this Block are executed and will modify the
Block contents.
Bit
Bit Name
Value
Function
7-5
Reserved
4
GPI4
‘1’
Input Pin GPI4 is at V
IH
‘0’
Input Pin GPI4 is at V
IL
3
GPI3
‘1’
Input Pin GPI3 is at V
IH
‘0’
Input Pin GPI3 is at V
IL
2
GPI2
‘1’
Input Pin GPI2 is at V
IH
‘0’
Input Pin GPI2 is at V
IL
1
GPI1
‘1’
Input Pin GPI1 is at V
IH
‘0’
Input Pin GPI1 is at V
IL
0
GPI0
‘1’
Input Pin GPI0 is at V
IH
‘0’
Input Pin GPI0 is at V
IL
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