參數資料
型號： M50LPW116N1T
廠商： 意法半導體
英文描述： 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory
中文描述： 16兆位的2Mb × 8，啟動塊3V電源低引腳數快閃記憶體
文件頁數： 15/36頁
文件大?。?/td> 259K
代理商： M50LPW116N1T
15/36
M50LPW116
Erase Status (Bit 5).
The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block(s)
and still failed to verify that the block(s) has erased
correctly. The Erase Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Erase Status bit is ‘0’ the memory has
successfully verified that the block(s) has erased
correctly; when the Erase Status bit is ‘1’ the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the block(s) and still failed to
verify that the block(s) has erased correctly.
Once the Erase Status bit is set to ‘1’ it can only be
reset to ‘0’ by a Clear Status Register command or
a hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
sued, otherwise the new command will appear to
fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong
command sequence has been attempted).
Program Status (Bit 4).
The Program Status bit
can be used to identify if the memory has applied
the maximum number of program pulses to the
byte and still failed to verify that the byte has pro-
grammed correctly. The Program Status bit should
be read once the Program/Erase Controller Status
bit is ‘1’ (Program/Erase Controller inactive).
When the Program Status bit is ‘0’ the memory has
successfully verified that the byte has pro-
grammed correctly; when the Program Status bit is
‘1’ the Program/Erase Controller has applied the
maximum number of pulses to the byte and still
failed to verify that the byte has programmed cor-
rectly.
Once the Program Status bit is set to ‘1’ it can only
be reset to ‘0’ by a Clear Status Register com-
mand or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong
command sequence has been attempted).
V
PP
Status (Bit 3).
The V
PP
Status bit can be
used to identify an invalid voltage on the V
PP
pin
during Program and Erase operations. The V
PP
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc-
cur if V
PP
becomes invalid during a Program or
Erase operation.
When the V
PP
Status bit is ‘0’ the voltage on the
V
PP
pin was sampled at a valid voltage; when the
V
PP
Status bit is ‘1’ the V
PP
pin has a voltage that
is below the V
PP
Lockout Voltage, V
PPLK
, the
memory is protected; Program and Erase opera-
tion cannot be performed. (The V
PP
status bit is ‘1’
if a Quadruple Byte Program command is issued
and the V
PP
signal has a voltage less than V
PPH
applied to it.)
Once the V
PP
Status bit set to ‘1’ it can only be re-
set to ‘0’ by a Clear Status Register command or a
hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
sued, otherwise the new command will appear to
fail.
Program Suspend Status (Bit 2).
The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Program Suspend Status bit is ‘0’ the
Program/Erase Controller is active or has complet-
ed its operation; when the bit is ‘1’ a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1).
The Block Pro-
tection Status bit can be used to identify if the Pro-
gram or Block Erase operation has tried to modify
the contents of a protected block. When the Block
Protection Status bit is to ‘0’ no Program or Block
Erase operations have been attempted to protect-
ed blocks since the last Clear Status Register
command or hardware reset; when the Block Pro-
tection Status bit is ‘1’ a Program or Block Erase
operation has been attempted on a protected
block.
Once it is set to ‘1’ the Block Protection Status bit
can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If it is set to ‘1’ it
should be reset before a new Program or Block
Erase command is issued, otherwise the new
command will appear to fail.
Using the A/A Mux Interface the Block Protection
Status bit is always ‘0’.
Reserved (Bit 0).
Bit 0 of the Status Register is
reserved. Its value should be masked.
LOW PIN COUNT (LPC) INTERFACE
CONFIGURATION REGISTERS
When the Low Pin Count Interface is selected sev-
eral additional registers can be accessed. These
registers control the protection status of the Blocks
and read the General Purpose Input pins. See Ta-
ble 14 for an example of the Register Configura-
tion map, valid for the boot memory, i.e. ID0-ID3
floating or driven L
OW
, V
IL
and A21, A23-A25 set
to ‘1’.
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