參數(shù)資料
型號(hào): M44C090-XXX-FL16
廠(chǎng)商: TEMIC SEMICONDUCTORS
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDSO16
文件頁(yè)數(shù): 6/319頁(yè)
文件大?。?/td> 11009K
代理商: M44C090-XXX-FL16
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)第310頁(yè)第311頁(yè)第312頁(yè)第313頁(yè)第314頁(yè)第315頁(yè)第316頁(yè)第317頁(yè)第318頁(yè)第319頁(yè)
103
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag
according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for
updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a
low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value
written to OCRnA or ICRn is lower than the current value of TCNTn, the counter will miss the compare match. The counter will
then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In
many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCRnA for defining TOP
(WGMn3:0 = 15) since the OCRnA then will be double buffered.
For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each compare match
by setting the compare output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin
unless the data direction for the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum frequency
of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The waveform frequency is defined by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the normal mode of operation, the TOVn flag is set in the same timer clock cycle that the counter counts from MAX to
0x0000.
13.8.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform
generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from
BOTTOM to TOP then restarts from BOTTOM. In non-inverting compare output mode, the output compare (OCnx) is set on the
compare match between TCNTn and OCRnx, and cleared at TOP. In inverting compare output mode output is cleared on
compare match and set at TOP. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice
as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency
makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows
physically small sized external components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution
allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM
resolution in bits can be calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or
0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is
then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 13-7. The figure
shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a
histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small
horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx interrupt flag
will be set when a compare match occurs.
f
OCnA
f
clk_I/O
2 N
1
OCRnA
+
()
--------------------------------------------------
=
R
FPWM
TOP
1
+
()
log
2
()
log
----------------------------------
=
相關(guān)PDF資料
PDF描述
M44C090-XXX-DIT 4-BIT, MROM, 4 MHz, MICROCONTROLLER, UUC
M48ST59W-70MH1TR 0 TIMER(S), REAL TIME CLOCK, PDSO44
M48ST59W-100MH1 0 TIMER(S), REAL TIME CLOCK, PDSO44
M48T02-150PC1 0 TIMER(S), REAL TIME CLOCK, PDIP24
M48T18-100MH1TR 0 TIMER(S), REAL TIME CLOCK, PDSO28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M44C890 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:Low-Current Microcontroller for Wireless Communication
M44C890-H 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:Low-Current Microcontroller for Wireless Communication
M44S05K4F1 功能描述:汽車(chē)連接器 MX44 Terminals RoHS:否 制造商:Amphenol SINE Systems 產(chǎn)品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風(fēng)格: 端接類(lèi)型: 觸點(diǎn)電鍍:Nickel
M44T332538880MHZ 制造商:MEC 功能描述:
M44T3338880MHZ 制造商:MEC 功能描述: