304
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
0x38 (0x58)
Reserved
–
0x37 (0x57)
SPMCSR
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
0x36 (0x56)
Reserved
–
0x35 (0x55)
MCUCR
SPIPS
–
–PUD
–
IVSEL
IVCE
0x34 (0x54)
MCUSR
–
WDRF
BORF
EXTRF
PORF
0x33 (0x53)
SMCR
–
SM2
SM1
SM0
SE
0x32 (0x52)
MSMCR
Monitor Stop Mode Control Register
Reserved
0x31 (0x51)
MONDR
Monitor Data Register
Reserved
0x30 (0x50)
ACSR
AC3IF
AC2IF
AC1IF
AC0IF
AC3O
AC2O
AC1O
AC0O
0x2F (0x4F)
Reserved
–
0x2E (0x4E)
SPDR
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
0x2D (0x4D)
SPSR
SPIF
WCOL
–
–SPI2X
0x2C (0x4C)
SPCR
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
0x2B (0x4B)
Reserved
–
0x2A (0x4A)
Reserved
–
0x29 (0x49)
PLLCSR
-
PLLF
PLLE
PLOCK
0x28 (0x48)
OCR0B
OCR0B7
OCR0B6
OCR0B5
OCR0B4
OCR0B3
OCR0B2
OCR0B1
OCR0B0
0x27 (0x47)
OCR0A
OCR0A7
OCR0A6
OCR0A5
OCR0A4
OCR0A3
OCR0A2
OCR0A1
OCR0A0
0x26 (0x46)
TCNT0
TCNT07
TCNT06
TCNT05
TCNT04
TCNT03
TCNT02
TCNT01
TCNT00
0x25 (0x45)
TCCR0B
FOC0A
FOC0B
–
WGM02
CS02
CS01
CS00
0x24 (0x44)
TCCR0A
COM0A1
COM0A0
COM0B1
COM0B0
–
–WGM01
WGM00
0x23 (0x43)
GTCCR
TSM
ICPSEL1
–
PSRSYNC
0x22 (0x42)
EEARH
–
EEAR9
EEAR8
0x21 (0x41)
EEARL
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
0x20 (0x40)
EEDR
EEDR7
EEDR6
EEDR5
EEDR4
EEDR3
EEDR2
EEDR1
EEDR0
0x1F (0x3F)
EECR
–
EERIE
EEMWE
EEWE
EERE
0x1E (0x3E)
GPIOR0
GPIOR07
GPIOR06
GPIOR05
GPIOR04
GPIOR03
GPIOR02
GPIOR01
GPIOR00
0x1D (0x3D)
EIMSK
–
INT3
INT2
INT1
INT0
0x1C (0x3C)
EIFR
–
INTF3
INTF2
INTF1
INTF0
0x1B (0x3B)
PCIFR
–
PCIF3
PCIF2
PCIF1
PCIF0
0x1A (0x3A)
GPIOR2
GPIOR27
GPIOR26
GPIOR25
GPIOR24
GPIOR23
GPIOR22
GPIOR21
GPIOR20
0x19 (0x39)
GPIOR1
GPIOR17
GPIOR16
GPIOR15
GPIOR14
GPIOR13
GPIOR12
GPIOR11
GPIOR10
0x18 (0x38)
Reserved
–
0x17 (0x37)
Reserved
–
29.
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64 loca-
tion reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations are
reserved.