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參數(shù)資料
| 型號(hào)： | M44C090-XXX-FL16 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDSO16 |
| 文件頁(yè)數(shù)： | 299/319頁(yè) |
| 文件大?。?/td> | 11009K |
| 代理商： | M44C090-XXX-FL16 |
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80
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
The OCR0x registers are double buffered when using any of the pulse width modulation (PWM) modes. For the normal and
clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the
update of the OCR0x compare registers to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has
access to the OCR0x buffer register, and if double buffering is disabled the CPU will access the OCR0x directly.
12.4.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force output
compare (FOC0x) bit. Forcing compare match will not set the OCF0x flag or reload/clear the timer, but the OC0x pin will be
updated as if a real compare match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or
toggled).
12.4.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 register will block any compare match that occur in the next timer clock cycle, even when
the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt
when the Timer/Counter clock is enabled.
12.4.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved
when changing TCNT0 when using the output compare unit, independently of whether the Timer/Counter is running or not. If
the value written to TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting.
The setup of the OC0x should be performed before setting the data direction register for the port pin to output. The easiest way
of setting the OC0x value is to use the force output compare (FOC0x) strobe bits in normal mode. The OC0x registers keep their
values even when changing between waveform generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will
take effect immediately.
12.5
Compare Match Output Unit
The compare output mode (COM0x1:0) bits have two functions. The waveform generator uses the COM0x1:0 bits for defining
the output compare (OC0x) state at the next compare match. Also, the COM0x1:0 bits control the OC0x pin output source.
Figure 12-4 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by
the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x register, not the OC0x
pin. If a system reset occur, the OC0x register is reset to “0”.
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