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參數(shù)資料
| 型號： | M41ST85WMH6TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.300 INCH, SNAPHAT, PLASTIC, SOH-28 |
| 文件頁數(shù)： | 19/41頁 |
| 文件大?。?/td> | 376K |
| 代理商： | M41ST85WMH6TR |
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Clock operation
M41ST85W
3.8
Reset inputs (RSTIN1 & RSTIN2)
The M41ST85W provides two independent inputs which can generate an output reset. The
duration and function of these resets is identical to a reset generated by a power cycle.
than tRLRH1 and tRLRH2 will not generate a reset condition. RSTIN1 and RSTIN2 are each
internally pulled up to VCC through a 100 kΩ resistor.
Figure 17.
RSTIN1 & RSTIN2 timing waveforms
Note:
With pull-up resistor
Table 5.
Reset AC characteristics
3.9
Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (1.25 V). If PFI is less
than the power-fail threshold (VPFI), the power-fail output (PFO) will go low. This function is
intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is
connected through an external voltage divider (see Figure 5 on page 11) to either the
unregulated DC input (if it is available) or the regulated output of the VCC regulator. The
voltage divider can be set up such that the voltage at PFI falls below VPFI several
milliseconds before the regulated VCC input to the M41ST85W or the microprocessor drops
below the minimum operating voltage.
During battery backup, the power-fail comparator turns off and PFO goes (or remains) low.
This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high,
irrespective of VPFI for the write protect time (trec), which is the time from VPFD(max) until the
inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6 V (except where noted).
Min
Max
Unit
tRLRH1
(2)
2.
Pulse width less than 50 ns will result in no RESET (for noise immunity).
RSTIN1 low to RSTIN1 high
200
ns
tRLRH2
(3)
3.
Pulse width less than 20 ms will result in no RESET (for noise immunity).
RSTIN2 low to RSTIN2 high
100
ms
tR1HRH
(4)
4.
Programmable (see Table 6 on page 28).
RSTIN1 high to RST high
40
200
ms
tR2HRH
RSTIN2 high to RST high
40
200
ms
AI03665
RSTIN2
RST
(1)
RSTIN1
tRLRH1
tRLRH2
tR1HRH
tR2HRH
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