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參數(shù)資料
| 型號(hào)： | M39832-B12WNE1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | TVS UNI-DIR 30V 600W DO-15 |
| 中文描述： | 單芯片8兆1兆x8或512KB的x16閃存和256千位并行EEPROM存儲(chǔ)器 |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 253K |
| 代理商： | M39832-B12WNE1T |
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Under these conditions, reading the data output will
yield 01h if the block defined by the inputs on
A12-A18 is protected. Any attempt to program or
erase a protected block will be ignored by the
device.
Remarks:
– The Verify operation is a read with a simulated
worst case conditions. This allows a guarantee
of the retention of the Protection status
– During the application life, the block protection
status can be accessed with a regular Read
instruction without applying a "high voltage" V
ID
on A9. This instruction is detailed in Table 5 and
Table 8.
Blocks Unprotection (See Figure 9).
All protected
blocks can be unprotected simultaneously on pro-
gramming equipment to allow updating of bit con-
tents. All blocks must first be protected before the
unprotection operation. Block unprotection is acti-
vated when A9, G and E are at V
ID
and A12, A15
at V
IH
. Unprotection is initiated by the edge of W
falling to V
IL
. After a delay of 10ms, the unprotection
operation will end. Unprotection verify is achieved
by bringing G and E to V
IL
while A0 is at V
IL
, A6 and
A1 are at V
IH
and A9 remains at V
ID
. In these
conditions, reading the output data will yield 00h if
the block defined by the inputs A12-A18 has been
succesfully unprotected. Each block must be sepa-
rately verified by giving its address in order to
ensure that it has been unprotected.
Remarks:
– The Verify operation is a read with a simulated
worst case conditions. This allows a guarantee
of the retention of the Protection status
– During the application life, the Block protection
status can be accessed with a regular Read
instruction without "high voltage" V
ID
on A9. This
instruction is detailed in Table 5 and Table 8.
Block Temporary Unprotection.
Any previously
protected block can be temporarily unprotected in
order to change stored data. The temporary un-
protection mode is activated by bringing RP to V
ID
.
During the temporary unprotection mode the pre-
viously protected blocks are unprotected. A block
can be selected and data can be modified by
executing the Erase or Program instruction with the
RP signal held at V
ID
. When RP is returned to VIH,
all the previously protected blocks are again pro-
tected.
Read/Reset (RD) Instruction.
The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by the
two Coded cycles. Subsequent read operations will
read the memory array addressed and output the
data read. A wait state of 10ms is necessary after
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instruction is
given.
GLOSSARY
Array:
EEPROM array (256 Kbit) or Flash array (8
Mbit)
Block:
part of the Flash array (See Figure 3A and
3B).
Page:
64 bytes of EEPROM
Write and Program:
Writing (into the EEPROM
array) and programming (the Flash array is not
performed in a similar way:
– the Flash memory requires an instruction (see
Instruction chapter) for Erasing and another in-
struction for Programming one (or more) byte(s)
or word(s)
– the EEPROM memory is directly written with a
simple operation (see Operation chapter).
SDP:
Software Data Protection. Used for protect-
ing the EEPROM array against false Write opera-
tions (as in noisy environments).
POWER SUPPLY and CURRENT CONSUMP-
TION
Power Up.
The M39832 internal logic is reset upon
a power-up condition to Read memory status. Any
Write operation in EEPROM is inhibited during the
first 5 ms following the power-up.
Either EF, EE or W must be tied to V
IH
during
Power-up for the maximum security of the data
contents and to remove the possibility of a byte
being written on the first rising edge of EF, EE or
W. Any write cycle initiation is locked when Vcc is
below V
LKO
.
Supply Rails.
Normal precautions must be taken
for supply voltage decoupling, each device in a
system should have the V
CC
rail decoupled with a
0.1
μ
F capacitor close to the V
CC
and V
SS
pins. The
printed circuit board trace width should be sufficient
to carry the V
CC
program and erase currents re-
quired.
22/36
M39832
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M39832-B15WNE1T | TVS BI-DIR 30V 600W DO-15 |
| M39832-T12WNE6T | TVS UNI-DIR 33V 600W DO-15 |
| M39832-T15WNE6T | TVS BI-DIR 33V 600W DO-15 |
| M39832-B12WNE6T | RECTIFIER, BRIDGE, 600V, 6A, PB-6 |
| M39832-B15WNE6T | TVS UNI-DIR 51V 600W DO-15 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M39832-B12WNE6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M39832-B15WNE1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M39832-B15WNE6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M39832NE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M39832-T12WNE1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
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