參數(shù)資料
型號: M38C29FFAFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 5 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 52/104頁
文件大?。?/td> 1327K
代理商: M38C29FFAFP
Rev.2.00
May 28, 2004
page 49 of 100
38C2 Group (A Version)
CLOCK GENERATING CIRCUIT
The 38C2 group has two built-in oscillation circuits; main clock XIN
XOUT and sub-clock XCIN–XCOUT. An oscillation circuit can be formed
by connecting a resonator between XIN and XOUT (XCIN and XCOUT).
Use the circuit constants in accordance with the resonator
manufacturer’s recommended values. No external resistor is needed
between XIN and XOUT since a feedback resistor exists on-chip. How-
ever, an external feedback resistor is needed between XCIN and
XCOUT.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub clock XCIN-XCOUT oscillation circuit can-
not directly input clocks that are externally generated. Accordingly,
be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts os-
cillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Frequency/8 Mode
The system clock
φ is the frequency of XIN divided by 8. After reset is
released, this mode is selected.
(2) Frequency/4 Mode
The system clock
φ is the frequency of XIN divided by 4.
(3) Frequency/2 Mode
The system clock
φ is the frequency of XIN divided by 2.
(4) Low-speed Mode
The system clock
φ is the frequency of XCIN divided by 2. In the low-
speed mode, the low-power dissipation operation can be performed
when the main clock XIN is stopped by setting the bit 7 of the CPU
mode register to “0”. In this case, when main clock XIN oscillation is
restarted, generate the wait time until the oscillation is stable by pro-
gram after the bit 7 of the CPU mode register is set to “ 1” .
Fig. 50 Ceramic resonator circuit
Fig. 51 External clock input circuit
XOUT
CIN
COUT
CCIN
CCOUT
Rf
XCIN
XCOUT
XIN
Rd
(Note)
Note: An external feed-back resistor may be
needed depending on conditions.
s Notes on Clock Generating Circuit
If you switch the mode between frequency/2/4, or 8 and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode, set the
frequency in the condition that f(XIN) > 3 f(XCIN).
Oscillation Control
(1) Stop Mode
If the STP instruction is executed, the system clock
φ stops at an “H”
level, and main clock and sub-clock oscillators stop.
In this time, values set previously to timer 1 latch and timer 2 latch
are loaded automatically to timer 1 and timer 2. Set the values to
generate the wait time required for oscillation stabilization to timer 1
latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8
bits of timer 2) before the STP instruction.
The frequency divider for timer 1 is used for the timer 1 count source,
and the output of timer 1 is forcibly connected to timer 2. In this time,
bits 0 to 5 of the timer 12 mode register are cleared to “ 0” .
The values of the timer 12 frequency divider selection register are
not changed.
Set the interrupt enable bits of the timer 1 and timer 2 to disabled
(“ 0” ) before executing the STP instruction.
Oscillator restarts when reset occurs or an interrupt request is re-
ceived, but the system clock
φ is not supplied to the CPU until timer 2
underflows. This allows time for the clock circuit oscillation to stabi-
lize.
(2) Wait Mode
If the WIT instruction is executed, only the system clock
φ stops at an
“H” state. The states of main clock and sub clock are the same as the
state before executing the WIT instruction, and oscillation does not
stop. Since supply of system clock
φ is started immediately after the
interrupt is received, the instruction can be executed immediately.
XCOUT
XIN
XOUT
VCC
VSS
Open
External oscillation
circuit
Rd
Rf
CCOUT
CCIN
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